Computational Storage eBPF Processor Core
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Solution Overview
Problem
Existing computational storage devices using Extended Berkeley Packet Filter (eBPF) face inefficiencies due to slow interpretation and translation of instructions on modern embedded processors like ARM and RISC-V, leading to suboptimal performance in computational storage applications.
Innovation Solution
Implementing a computational storage device with pre-programmed slots that utilize an eBPF processor core within an ASIC, allowing native execution of eBPF instructions and optimizing performance by generating native instruction sets, and dynamically translating instructions to reduce latency and processing load.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If eBPF instructions are interpreted or translated on modern embedded processors (ARM, RISC-V), then computational storage functionality is achieved, but processing performance is slow and latency is high
Solution Approach 1:
The patent replaces the software-based interpretation and translation mechanisms with a hardware-based eBPF processor core that natively executes eBPF instructions. This substitution of mechanical/software systems with a dedicated hardware processor eliminates the performance overhead and latency associated with instruction interpretation and translation on general-purpose embedded processors.
Solution Approach 2:
The patent changes the execution parameter of eBPF instructions from interpreted/translated execution to native hardware execution. By modifying how eBPF instructions are processed - from software interpretation to hardware-native execution - the system achieves significant performance improvement and reduced latency.
2Productivity
If dedicated processor core is implemented for eBPF execution, then processing efficiency is improved, but device complexity increases
Solution Approach 1:
The eBPF processor core is designed to handle multiple computational storage tasks and workloads through a single unified hardware processor. This multi-functional design allows the device to execute various eBPF programs for different applications (data filtering, compression, encryption, etc.) without requiring separate dedicated hardware for each function, thereby managing complexity while maintaining versatility.
Solution Approach 2:
The patent uses pre-programmed computing instruction set slots that can be loaded with different eBPF programs. This copying approach allows the same hardware processor to execute multiple different computational programs by loading them from pre-programmed slots, achieving functional diversity without increasing hardware complexity.
3Speed
If instructions are dynamically translated to native instruction sets, then execution speed is improved, but processing overhead and bandwidth usage increase
Solution Approach 1:
The patent pre-programs computing instruction sets in dedicated slots before runtime. This preliminary action allows the system to have translation and compilation done in advance, so that during execution, the eBPF processor core can directly execute native instructions without real-time translation overhead, reducing both energy consumption and bandwidth usage during operation.
Data Source
AI summary
The technology disclosed herein provides a method including determining one or more dedicated computations storage programs (CSPs) used in a target market for a computational storage device, storing the dedicated CSPs in one or more pre-programmed computing instruction set (CIS) slots in the computational storage device, translating one or more instructions of the dedicated CSPs for processing using a native processor, loading one or more instructions of programmable CSPs to a CSP processor implemented within an application specific integrated circuit (ASIC) of the computational storage device, and processing the one or more instructions of the programmable CSPs using the CSP processor.