Computational Storage Controller Host Command Offloading
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in reducing costs and improving performance, particularly in managing computations and applications within storage devices, which burdens the host device and affects overall system performance.
Innovation Solution
A computational storage device is introduced, featuring a non-volatile memory device and a storage controller that includes a computation engine, a host interface block, a flash translation layer, and a memory interface block. This configuration allows for internal applications to generate internal commands, process host commands, and perform address mapping operations, thereby offloading computations from the host device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If storage devices support various computations or applications, then the computational burden on host devices is reduced, but the device complexity increases
Solution Approach 1:
The patent combines computation engine, application executor, and storage controller into a single integrated storage device. The computation engine executes applications that generate I/O commands, which are then processed by the storage controller along with host commands. This merging of computational and storage functions within one device reduces the computational burden on host devices while managing complexity through integrated design.
Solution Approach 2:
The storage device is designed with multi-functionality, serving both as a storage medium and a computational unit. The computation engine can execute various applications (file system, database, etc.) while the storage controller manages both host I/O and internally generated I/O commands. This universal design allows the device to perform multiple functions without requiring separate host processing for computational tasks.
2Productivity
If a computation engine executes internal applications to generate internal commands, then processing efficiency is improved, but the device complexity increases
Solution Approach 1:
The storage controller integrates multiple functions including host interface block, flash translation layer, memory interface block, and computation engine coordination. Instead of separate components for handling host commands and internal application commands, the controller merges these processing paths into a unified structure that efficiently manages both types of commands through shared resources and coordinated operation.
3Measurement precision
If the host interface block individually processes host commands and internal commands, then command processing accuracy is improved, but the processing time increases
Solution Approach 1:
The host interface block segments command processing into distinct pathways for host commands and internal commands generated by the computation engine. Each command type is individually processed through appropriate handling routines, ensuring accuracy while maintaining efficient processing flow. The segmentation allows parallel or sequential processing without interference between different command sources.
Data Source
AI summary
A computational storage device includes a non-volatile memory (NVM) device; and a storage controller configured to control the NVM device. The storage controller includes: a computation processor configured to execute an internal application to generate an internal command; a host interface circuit configured to receive a host command from an external host device, to receive the internal command from the computation processor, and to individually process the received host command and the received internal command; a flash translation layer (FTL) configured to perform an address mapping operation based on a result of the processing of the host interface circuit; and a memory interface circuit configured to control the NVM device based on the address mapping operation of the FTL.