Computational Storage Processor Message Queues for CPU Offloading

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Solution Overview

Problem

Conventional network-attached storage devices are inefficient due to the CPU being a bottleneck in processing power and communication bandwidth, especially when scaling up storage capacity, as they require data messages to flow through the CPU, which places a high burden on processing power and memory.

Innovation Solution

Implementing different processing paths for control messages and data messages, where control messages are routed through a processing device for administrative and management operations, while data messages are communicated directly between a storage device and a storage client without going through the processing device, reducing the workload on the CPU and improving efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If data messages flow through the CPU in conventional network-attached storage devices, then administrative control and security are maintained, but processing power and communication bandwidth are bottlenecked

Engineering Contradiction:
Improveadministrative controlVSAvoidprocessing power
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent segments message handling into two distinct paths: control messages are routed through the CPU for administrative processing, while data messages are routed directly between the storage device and network interface. This segmentation allows the CPU to focus only on control functions, eliminating it as a bottleneck for data processing while maintaining security through controlled access paths.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a message queue as an intermediary mechanism that enables direct communication between the storage device and network interface for data messages. This intermediary structure allows data to flow without CPU involvement while still maintaining system coordination and security through the controlled queue interface.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Quantity of substance

If storage capacity is scaled up in conventional devices, then more storage space is available, but the burden on CPU processing power and memory increases

Engineering Contradiction:
Improvestorage capacityVSAvoidprocessing power burden
Core Design Contradiction:
Quantity of substanceVSUse of energy by moving object

Solution Approach 1:

By separating control message handling from data message processing, the system allows storage capacity to scale independently of CPU processing requirements. The CPU only handles control plane traffic, while data plane traffic flows directly through the storage device and network interface, enabling storage scaling without proportional increases in processing burden.

Inventive Principle:
Principle #1Segmentation

3Ease of operation

If the CPU processes all messages, then centralized control is maintained, but power consumption and communication bandwidth requirements increase

Engineering Contradiction:
Improvecentralized controlVSAvoidpower consumption
Core Design Contradiction:
Ease of operationVSUse of energy by stationary object

Solution Approach 1:

The patent extracts data message processing from the CPU's responsibilities, creating a dedicated path for data traffic. This extraction reduces the CPU's processing burden and associated power consumption while maintaining centralized control through the separate control message path that still flows through the CPU.

Inventive Principle:
Principle #2Taking out (Extraction)

4Productivity

If data messages flow through the CPU, then centralized processing is maintained, but security is compromised by direct CPU access to data

Engineering Contradiction:
Improveprocessing efficiencyVSAvoidsecurity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent segments message routes to create a dedicated data message path that bypasses the CPU, preventing direct CPU access to data traffic. Control messages continue to flow through the CPU, maintaining security and administrative control, while data messages are handled securely through the isolated path between storage device and network interface.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20240069992A1Message Queues in Network-Ready Storage Products having Computational Storage Processors
Publication Date: 2024.02.29 MICRON TECHNOLOGY INC
  • US20240069992A1 patent drawing
  • US20240069992A1 patent drawing
  • US20240069992A1 patent drawing

AI summary

A storage product manufactured as a standalone computer component, having a bus connector to an external processor, a storage device, a random-access memory, a computational storage processor, and a processing device to identify, among storage access messages from a computer network, first messages, second messages, and third messages. The random-access memory hosts first queues shared between the processing device and the external processor, and second queues shared between the processing device and the computational storage processor. The processing device can place the first messages in the first queues for the external processor to generate fourth messages, place the second messages in the second queues for the computational storage processor to generate fifth messages, and provide the third messages to the storage device. The storage device can process the third messages, the fourth messages, and the fifth messages to implement requests in the storage access messages.