Computational Storage Queue Chaining for Low-Latency CSF Control
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Solution Overview
Problem
Conventional computational storage processors (CSPs) face inefficiencies due to high internal bandwidth requirements for memory reads and writes, especially when chaining multiple computational storage functions (CSFs), and high latency in data transfers between a host and CSP, which degrade performance and increase costs.
Innovation Solution
Implementing a CSF controller that dynamically chains CSFs and coordinates operations, using submission and completion queues to manage data transfers efficiently, reducing the need for external communication and internal bandwidth by scheduling multiple operations with a single command.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple computational storage functions (CSFs) are chained together to perform sequential operations, then functional capability and versatility are improved, but internal bandwidth requirements increase and performance degrades
Solution Approach 1:
The system segments the data processing workflow into independent computational storage function (CSF) units, each capable of performing specific operations. These segmented CSFs can be chained together to handle complex operations while maintaining efficient data flow through the system, avoiding the performance degradation associated with traditional sequential processing.
Solution Approach 2:
The patent introduces an intermediary mechanism (the system architecture that coordinates CSF operations) that enables direct data transfer between chained CSFs without requiring excessive internal bandwidth. This intermediary structure manages the data flow efficiently, allowing multiple CSFs to operate in sequence without proportionally increasing bandwidth requirements.
2Quantity of substance
If high bandwidth memory is used to address internal bandwidth requirements, then data transfer capacity is improved, but cost increases significantly
Solution Approach 1:
The system changes the operational parameters of the CSFs and their coordination mechanism to achieve efficient data processing without requiring high bandwidth memory. By optimizing how CSFs are chained and how data flows between them, the system maintains adequate data transfer capacity using standard memory components, thereby avoiding the significant cost increase associated with high bandwidth memory.
3Ease of operation
If host orchestrates data transfers between CSFs, then control and coordination are improved, but latency increases and performance degrades
Solution Approach 1:
The patent extracts the orchestration function from the host system and embeds it within the computational storage processor itself. This allows CSFs to be coordinated and managed directly at the storage device level, eliminating the need for continuous host intervention and significantly reducing the latency associated with host-CSP communication over networks.
Solution Approach 2:
The computational storage processor is designed to be self-sufficient, with the ability to orchestrate and coordinate data transfers between its own CSFs without external host control. This self-service capability enables autonomous operation of the CSF chain, reducing dependency on the host and minimizing communication latency.
Data Source
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AI summary
A computational storage processor (CSP) is provided that includes the CSP comprising a plurality of submission queues (SQs), a plurality of computational storage functions (CSFs), a CSF controller, and a CSP controller, and a method of controlling the CSP is provided that includes directing a first submission queue entry (SQE) that is written to a first one of the plurality of SQs to the CSF controller, generating, by the CSF controller, one or more secondary SQEs based on the first SQE, each of the one or more secondary SQEs is directed to a respective one of the CSFs, writing, by the CSF controller, the one or more secondary SQEs to a second one of the plurality of SQs, directing each of the one or more secondary SQEs to an associated respective one of the CSFs, and for each of the one or more secondary SQEs, performing, by the associated respective one of the CSFs, an operation associated with the secondary SQE.