Computational Storage Multi-Core Task Scheduling
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Solution Overview
Problem
Conventional computational storage devices do not distinguish between input/output (I/O) tasks and background tasks, leading to resource shortages and inefficient processing, as both tasks are often performed on the same processor core, resulting in delayed I/O task processing and suboptimal resource utilization.
Innovation Solution
A computational storage device with a multi-core processor and a task control module that generates and allocates I/O and background tasks separately to different cores based on their operational states, allowing for efficient core utilization by monitoring core activity and reallocating tasks to idle or less utilized cores.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a conventional computational storage device schedules I/O tasks and background tasks together on the same processor core, then the device structure remains simple, but the I/O task processing speed deteriorates due to resource shortage
Solution Approach 1:
The patent segments the task scheduling by separating I/O tasks and background tasks into different scheduling queues. The scheduler divides task management into distinct segments: an I/O task queue for user-requested operations and a background task queue for maintenance operations, allowing independent scheduling and resource allocation for each task type.
Solution Approach 2:
The patent applies local quality by assigning different scheduling priorities and resource allocation strategies to different task types. I/O tasks receive higher priority and dedicated core allocation to ensure fast response, while background tasks are scheduled with lower priority and can utilize idle cores, creating localized optimization for each task category.
2Device complexity
If a conventional computational storage device does not reallocate I/O tasks to idle cores, then the scheduling mechanism remains simple, but resource utilization deteriorates
Solution Approach 1:
The patent implements dynamic scheduling that continuously monitors processor core states and adjusts task allocation in real-time. When cores become idle, the scheduler dynamically reallocates pending I/O tasks to these freed cores, creating a flexible and adaptive scheduling mechanism that responds to changing system conditions.
Solution Approach 2:
The scheduler incorporates feedback mechanisms by monitoring the operational states of processor cores and using this information to make informed scheduling decisions. The system continuously gathers feedback on core availability and task completion status, then adjusts task allocation accordingly to optimize resource utilization.
3Device complexity
If both I/O tasks and background tasks are performed on the same processor core, then task management remains simple, but processing efficiency deteriorates
Solution Approach 1:
The patent segments task execution by creating separate scheduling queues for I/O tasks and background tasks. This segmentation allows the system to manage different task types independently, preventing background tasks from interfering with I/O task processing and improving overall processing efficiency.
Solution Approach 2:
The patent changes the scheduling parameter by introducing priority levels and core allocation strategies specific to task type. I/O tasks are assigned higher priority and can be allocated to dedicated cores, while background tasks use lower priority and share cores when idle, fundamentally changing how tasks are parameterized and scheduled.
Data Source
AI summary
A computational storage device includes a storage device and a computation control circuit. The computation control circuit includes multi-core processor and is configured to generate an input/output (I/O) task according to an I/O command, generate a background task according to the I/O command, select an idle core among a plurality of cores in the multi-core processor to perform the background task, and control the storage device. The computation control circuit may include a task control module configured to select the idle core.