Compute Brick Package Architecture for High-Bandwidth 3D Die Stacking
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Solution Overview
Problem
Current packaging architectures for multi-chip modules are limited in their ability to scale to next-generation servers with signal speeds greater than 10 GHz and data speeds of 3-10 Terabytes per second due to bandwidth reduction, signal delay, and signal distortion, primarily because IC dies are oriented parallel to each other and interconnected by conventional interconnects.
Innovation Solution
The IC dies are coupled such that one surface is orthogonal to another, with interconnects comprising oxide-oxide bonds and metal-metal bonds, and the metallization stack has conductive traces orthogonal to the first surface, allowing for a more efficient vertical stacking of dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If IC dies are oriented parallel to each other with conventional interconnects, then the packaging architecture is simple to manufacture, but bandwidth reduction and signal distortion occur at signal speeds greater than 10 GHz
Solution Approach 1:
The patent transitions from conventional parallel (2D) die arrangement to vertical (3D) stacking architecture. Dies are stacked vertically with interconnects extending through multiple die layers, enabling signals to travel shorter distances and reducing bandwidth reduction and distortion at high frequencies while maintaining manufacturing feasibility through adapted packaging processes
2Productivity
If IC dies are vertically stacked to reduce signal loss, then bandwidth and data transfer rates increase, but the complexity of interconnect fabrication increases
Solution Approach 1:
The interconnect structure is segmented into distinct functional layers: through-die vias for vertical connections between stacked dies, and trace layers for horizontal signal routing within each die. This segmentation allows independent optimization of vertical and horizontal interconnect paths, managing fabrication complexity while enabling high-speed data transfer through efficient signal pathways
3Quantity of substance
If more high-power compute IC dies are stacked within constrained footprint, then computing capacity increases, but heat dissipation becomes more challenging
Solution Approach 1:
Multiple high-power compute IC dies are nested vertically in a stacked configuration, with each die containing computational cores and associated interconnect structures. This nesting approach maximizes the number of compute dies within a constrained horizontal footprint, enabling increased computing capacity while managing thermal density through vertical distribution of heat-generating components
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the scalability and performance of compute walls by reducing signal loss and distortion, enabling higher bandwidth and data transfer rates, while allowing for more high-power compute IC dies to be stacked within a constrained footprint.
Implementation Method 1
interconnects comprising oxide-oxide bonds and metal-metal bonds
Implementation Method 2
interconnects comprising oxide-oxide bonds and metal-metal bonds
Data Source
AI summary
Embodiments of a microelectronic assembly comprise: a plurality of microelectronic sub-assemblies arranged in a coplanar array, each microelectronic sub-assembly having a first side and an opposing second side; a first conductive plate coupled to the first sides of the microelectronic sub-assemblies; and a second conductive plate coupled to the second sides of the microelectronic sub-assemblies. The first conductive plate and the second conductive plate comprise sockets corresponding to each of the microelectronic sub-assemblies, and each microelectronic sub-assembly comprises a first plurality of integrated circuit (IC) dies coupled on one end to a first IC die and on an opposing end to a second IC die; and a second plurality of IC dies coupled to the first IC die and to the second IC die.