Non-Volatile Memory Device With Compute-Enabled Buffer Endurance
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Solution Overview
Problem
Non-volatile memory circuits have a relatively low endurance, limited by the maximum number of write cycles each elementary storage cell can withstand.
Innovation Solution
A memory device is designed with an array of non-volatile memory cells coupled to a buffer memory circuit comprising volatile memory cells, which is adapted to implement calculation functions, thereby limiting access to the non-volatile memory cells and reducing wear.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If non-volatile memory cells are used for storage, then data retention and non-volatility are improved, but endurance (maximum number of write cycles) deteriorates
Solution Approach 1:
A buffer memory circuit is introduced as an intermediary between the processor and the non-volatile memory array. This buffer circuit absorbs write operations and manages data flow, reducing the number of write cycles that reach the non-volatile memory cells. The buffer acts as a mediator that protects the non-volatile memory from excessive write operations while maintaining data retention capabilities.
Solution Approach 2:
Data is pre-processed and staged in the buffer memory circuit before being written to the non-volatile memory array. This preliminary action in the buffer allows for optimization of write operations, such as coalescing multiple writes into fewer operations, thereby extending the endurance of the non-volatile memory cells while preserving data retention.
2Reliability
If buffer memory circuit is added to implement calculation functions, then endurance is improved, but device complexity increases
Solution Approach 1:
The buffer memory circuit is designed to serve multiple functions: it acts as a temporary storage buffer, implements calculation functions through integrated logic circuits, and manages data flow between the processor and non-volatile memory. This multi-functionality reduces the need for separate dedicated circuits, thereby limiting the increase in overall device complexity while improving endurance.
Solution Approach 2:
The calculation functions are merged directly into the buffer memory circuit structure, combining storage and processing capabilities in a single integrated unit. This merging eliminates the need for separate processing circuits and reduces interconnect complexity, allowing endurance improvement without proportionally increasing device complexity.
Data Source
Figure 1~2
AI summary
This description relates to a memory device (200) comprising: - a non-volatile memory circuit (101); - a buffer memory circuit (203) comprising a volatile memory circuit (221); - an input-output circuit (105); - a first data link (104) connecting the non-volatile memory circuit (101) to the buffer memory circuit (203); - a second data link (106) connecting the buffer memory circuit (203) to the input-output circuit (105); and - a control circuit (225), in which the buffer memory circuit (203) is adapted to implement calculations having as operands data stored in the volatile memory circuit (221).