Compute Enabled Cache Controller Block Select Metadata
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Solution Overview
Problem
Current cache architectures in computing systems do not effectively leverage the compute capability of processing-in-memory (PIM) devices, as they lack metadata for transparent alignment and placement of cache blocks across multiple locations, leading to inefficient data access and power consumption.
Innovation Solution
The implementation of a cache controller that creates block select and subrow select metadata to facilitate the alignment and placement of cache blocks within a cache memory, allowing for compute-enabled cache operations by controlling the placement of cache blocks across multiple rows and locations, thereby optimizing data access and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional cache architecture is used without compute capability, then device complexity is reduced, but processing efficiency and power utilization are insufficient
Solution Approach 1:
The patent combines cache memory functionality with compute capabilities by integrating sense amplifiers that can perform logical operations (AND, OR, NOT, NAND, NOR, XOR) directly on cached data. This merging allows the cache to function both as data storage and as a processing unit, improving productivity while managing device complexity through unified architecture design.
Solution Approach 2:
The sense amplifiers in the cache are designed to perform multiple functions: traditional data sensing/readout operations and computational logical operations. This multi-functionality allows the same hardware structure to serve both caching and processing roles, enhancing productivity without proportionally increasing device complexity.
2Use of energy by moving object
If compute operations are performed externally to the memory array, then device complexity is reduced, but power consumption and access time increase
Solution Approach 1:
The cache memory performs compute operations independently using its own sense amplifier circuitry without requiring external processing resources. The sense amplifiers execute logical operations directly on the data stored in the cache, allowing the system to serve its own processing needs and reducing power consumption associated with data transfer and external computation.
3Productivity
If cache blocks are stored without alignment metadata, then device complexity is reduced, but data access efficiency and parallelism are limited
Solution Approach 1:
The patent implements alignment metadata (block select and subrow select bits) that is prepared and stored in advance with cache blocks. This preliminary organization of data with accompanying alignment information enables efficient parallel access and compute operations later, as the alignment data is already available without requiring additional processing during data retrieval.
Data Source
AI summary
The present disclosure includes apparatuses and methods for compute enabled cache. An example apparatus comprises a compute component, a memory and a controller coupled to the memory. The controller configured to operate on a block select and a subrow select as metadata to a cache line to control placement of the cache line in the memory to allow for a compute enabled cache.