Compute Graph Scheduling via Sequence Space Optimization
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Solution Overview
Problem
The challenge lies in efficiently scheduling operations in computational graphs on resource-limited edge devices, where conventional approaches face difficulties due to high latency and memory constraints, especially when applying neural networks for tasks like image recognition and autonomous driving.
Innovation Solution
A processor-implemented method that receives a graph of nodes representing operations, determines sequences based on precedence constraints, selects sequences considering memory constraints, and generates a schedule for execution on the device, reducing the search space to optimize latency and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional heuristic strategies are used for scheduling operations, then the scheduling process is simple to implement, but latency and memory consumption are high
Solution Approach 1:
The patent segments the scheduling problem into two distinct phases: (1) sequence determination phase that identifies valid execution sequences based on precedence constraints, and (2) schedule generation phase that selects optimal sequences while satisfying memory constraints. This segmentation allows each phase to be optimized independently, reducing overall latency while maintaining implementation feasibility.
Solution Approach 2:
The patent introduces a sequence space dimension that transforms the traditional scheduling approach. Instead of directly searching through all possible schedules, the method first determines valid sequences in sequence space, then maps these sequences to actual schedules. This dimensional transformation reduces the search space complexity and enables more efficient optimization of latency.
2Ease of manufacture
If conventional heuristic strategies are used for scheduling operations, then the implementation is straightforward, but memory consumption is high
Solution Approach 1:
The patent segments the scheduling problem into two distinct phases: (1) sequence determination phase that identifies valid execution sequences based on precedence constraints, and (2) schedule generation phase that selects optimal sequences while satisfying memory constraints. This segmentation allows each phase to be optimized independently, reducing overall latency while maintaining implementation feasibility.
Solution Approach 2:
The patent performs preliminary action by determining all valid sequences based on precedence constraints before actual schedule generation. This pre-computation of sequence space enables the subsequent schedule generation phase to efficiently select sequences that satisfy memory constraints without having to re-evaluate precedence constraints during scheduling, thereby reducing memory consumption.
3Reliability
If the solution space for determining schedules is not reduced, then all possible schedules can be explored, but the search space becomes prohibitively large
Solution Approach 1:
The patent segments the scheduling problem into two distinct phases: (1) sequence determination phase that identifies valid execution sequences based on precedence constraints, and (2) schedule generation phase that selects optimal sequences while satisfying memory constraints. This segmentation allows each phase to be optimized independently, reducing overall latency while maintaining implementation feasibility.
Solution Approach 2:
The patent introduces a sequence space dimension that transforms the traditional scheduling approach. Instead of directly searching through all possible schedules, the method first determines valid sequences in sequence space, then maps these sequences to actual schedules. This dimensional transformation reduces the search space complexity and enables more efficient optimization of latency.
Data Source
AI summary
A processor-implemented method for generating a schedule for executing operations of a compute graph includes receiving a graph including multiples nodes connected by edges. Each of the multiple nodes represents an operation to be executed. A set of sequences for executing the nodes is determined based on one or more precedence constraints. One or more sequences are selected from the set of sequences based on a memory constraint associated with a device for executing the nodes. A schedule for executing the nodes on the device is generated based on the selected one or more sequences.