Compute Unit Group Startup to Mitigate IC Voltage Droop
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Solution Overview
Problem
Inductive-induced voltage droop and overshoot in integrated circuits cause operational failures due to large current ramps, which existing solutions like clock stretching negatively impact performance and incur additional costs.
Innovation Solution
Implement a statically reconfigurable dataflow architecture processor (SRDAP) with control circuitry that staggers the startup of compute units to manage current ramps, using a compiler to generate configuration information for optimal grouping and synchronization, thereby mitigating voltage droop and overshoot.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If compute units are started up simultaneously to maximize parallelism and productivity, then processing throughput is improved, but inductive-induced voltage droop occurs due to large current ramps
Solution Approach 1:
The compute units are divided into multiple groups, where each group is assigned a unique identifier. The control circuitry manages the startup of different groups sequentially rather than simultaneously, thereby segmenting the current ramp demand and preventing excessive voltage droop while maintaining overall system productivity.
Solution Approach 2:
The control circuitry pre-establishes group identifiers and startup sequences before operation begins. By determining the startup order in advance and enforcing it through control signals, the system prepares for controlled current ramps before they occur, avoiding voltage droop without sacrificing throughput.
2Reliability
If clock stretching is applied to reduce current ramp rate and mitigate voltage droop, then voltage stability is improved, but processing performance deteriorates
Solution Approach 1:
Instead of uniformly stretching the clock cycle for all compute units, the system dynamically controls the startup timing of different compute unit groups. This dynamic approach allows the system to manage current ramps effectively while maintaining optimal clock timing for active units, thus preserving processing performance while ensuring voltage stability.
Solution Approach 2:
The control circuitry implements periodic startup sequences for compute unit groups, where each group is activated in a predetermined sequence rather than continuously or simultaneously. This periodic activation pattern smooths the current demand over time, stabilizing voltage without requiring overall clock stretching that would reduce performance.
3Reliability
If additional circuitry is added to detect and respond to voltage droop dynamically, then voltage control capability is improved, but device complexity and cost increase
Solution Approach 1:
The control circuitry pre-assigns group identifiers to compute units and establishes startup sequences before operation begins. This preliminary configuration eliminates the need for complex real-time voltage sensing and dynamic response circuitry, as the voltage droop prevention is achieved through predetermined controlled startup sequences rather than reactive detection mechanisms.
Solution Approach 2:
Each compute unit is equipped with a control input that responds to control signals from the control circuitry. The system uses simple identifier matching and signal-based coordination rather than complex voltage detection circuitry, allowing the compute units to self-regulate their startup timing based on control signals, thereby reducing overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces operational failures by managing current ramps without performance degradation, eliminating the need for costly hardware solutions and dynamic clock adjustments.
Implementation Method 1
the voltage drop across an inductive load is the product of the inductance of the load and the time rate of change of the current drawn through the inductive loads, which may be expressed in equation (1) below in which L is the inductance of the load and di/dt is the first derivative of the current with respect to time through the load
Data Source
AI summary
An integrated circuit (IC) includes an array of statically reconfigurable compute units for separation into mutually exclusive groups. Each group includes statically reconfigurable number of compute units. Each compute unit includes a register statically reconfigurable with a group identifier that identifies which group the compute unit belongs to, a counter statically reconfigurable to synchronously increment with the counters of all the other compute units such that all the counters have the same value each clock cycle, and control circuitry that prevents the compute unit from starting to process data until the counter value matches the identifier. According to operation of the register, the counter, and the control circuitry, no more than the statically reconfigurable number of the compute units are allowed to start processing data concurrently to mitigate supply voltage droop caused by a time rate of change of current drawn by the IC through inductive loads of the IC.