Compute-in-Memory Package with Immersed Logic Dies
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Solution Overview
Problem
Current integrated circuit packages face limitations in computing efficiency, bandwidth, and latency due to the separation of logic and memory dies, which can be improved by integrating them in a closer proximity and efficient layout.
Innovation Solution
The formation of a compute-in-memory package with multiple tiers, where logic dies are immersed in memory dies and vice versa, using direct dielectric or hybrid bonding, and through-vias for electrical coupling, along with metal pillars and solder regions for enhanced connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If logic dies and memory dies are separated in conventional packages, then manufacturing and testing are easier, but computing efficiency decreases and latency increases
Solution Approach 1:
The patent implements compute-in-memory packaging where logic dies are physically immersed within memory dies, creating a nested configuration. This nesting allows logic units to be surrounded by memory cells, dramatically reducing access latency and increasing computing efficiency by eliminating traditional memory access bottlenecks.
Solution Approach 2:
The patent transitions from conventional 2D side-by-side die arrangement to 3D stacked and immersed configurations. Multiple tiers of dies are bonded together with logic dies positioned within memory die stacks, utilizing vertical space to achieve closer proximity between compute and memory units without increasing planar footprint.
2Productivity
If more device dies are integrated in the same package, then functionality and bandwidth increase, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent divides the integrated circuit system into multiple functional tiers, with each tier containing specific combinations of logic dies and memory dies. This segmentation allows for modular assembly and testing, where each tier can be independently characterized before final integration, reducing overall manufacturing complexity despite high die counts.
Solution Approach 2:
The patent creates multi-functional die structures where memory dies serve dual purposes: storing data and providing structural support for immersing logic dies. Similarly, logic dies perform both computation and act as interconnect elements within the tiered architecture, reducing the need for separate dedicated interconnect structures.
3Loss of time
If logic dies are immersed in memory dies, then access time decreases and computing efficiency increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent performs preliminary bonding of memory dies in stacks before immersing logic dies within the inter-die gaps. This sequential approach allows each memory die stack to be pre-aligned and bonded, creating stable structural units that simplify the subsequent logic die immersion process and reduce overall alignment complexity.
Solution Approach 2:
The patent introduces intermediary bonding structures and alignment features at die interfaces that facilitate precise positioning of logic dies within memory die stacks. These intermediary elements act as mechanical guides and electrical connectors, enabling accurate alignment while accommodating manufacturing tolerances.
Data Source
AI summary
A method includes placing a first plurality of dies over a carrier. The first plurality of dies include at least a first logic die and a first memory die, placing a second plurality of dies over the first plurality of dies. The second plurality of dies are electrically coupled to the first plurality of dies, and include at least a second logic die and a second memory die. A third plurality of dies are placed over the second plurality of dies, and are electrically coupled to the first plurality of dies and the second plurality of dies. The third plurality of dies include at least a third logic die and a third memory die. The method further includes forming electrical connectors over and electrically coupling to the first plurality of dies, the second plurality of dies, and the third plurality of dies.