Compute Kernel Logic Generation with Heterogeneous Clocking
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Solution Overview
Problem
Existing computing architectures, such as FPGAs, suffer from suboptimal power and resource utilization due to homogeneous clocking strategies that do not account for the varying computational demands of different logic elements, leading to inefficient tradeoffs between performance and power consumption.
Innovation Solution
Implementing a heterogeneous clocking strategy through compiler analysis and device telemetry to allow different clock frequencies for different logic elements within a computing architecture, optimizing power and resource consumption without degrading system-level performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single clock frequency is used for all logic elements, then system simplicity is maintained, but power consumption increases and resource utilization becomes inefficient
Solution Approach 1:
The patent segments the computing architecture into multiple independently clockable regions or modules. Each region can be assigned a different clock frequency based on its computational demands, allowing non-critical regions to run at lower frequencies to save power while critical regions maintain high frequencies for performance.
Solution Approach 2:
Different regions of the computing architecture are assigned different clock frequencies according to their specific performance requirements. Critical paths receive higher frequencies for optimal performance, while non-critical paths operate at reduced frequencies to minimize power consumption, creating a heterogeneous clocking strategy.
2Productivity
If clock frequency is maximized for performance-critical regions, then system performance improves, but power consumption and resource utilization costs increase for non-critical regions
Solution Approach 1:
The clocking strategy dynamically adjusts frequencies based on the operational status and performance requirements of different regions. The system can reconfigure clock frequencies at runtime based on workload characteristics, allowing optimization between performance and power consumption for each region independently.
Solution Approach 2:
The patent changes the clock frequency parameter differently across various regions of the computing architecture. By assigning higher frequencies to performance-critical regions and lower frequencies to non-critical regions, the system optimizes the trade-off between overall performance and power consumption.
3Ease of manufacture
If homogeneous clocking is used, then implementation simplicity is maintained, but the mapping between logic elements and application becomes opaque and suboptimal
Solution Approach 1:
The system incorporates feedback mechanisms that monitor performance and power consumption characteristics of different logic regions. This feedback information is used to automatically adjust clock frequencies and optimize the mapping between logic elements and application tasks, improving performance per watt while maintaining manageable implementation complexity.
Data Source
AI summary
Examples relate to an apparatus, device, method, and computer program for generating logic to be performed by computing circuitry of a computing architecture. The apparatus is configured to determine a performance-critical compute path of a compute kernel to be executed on a plurality of units of computing circuitry of a computing architecture, the compute kernel comprising a plurality of interdependent groups of computational instructions, with the performance-critical compute path being based on a subset of the interdependent groups of computational instructions. The apparatus is configured to determine, for at least one group of computational instructions outside the performance-critical compute path, a reduced clock frequency being lower than a maximally feasible clock frequency of the respective group of computational instructions. The apparatus is configured to generate logic to be performed by one or more of the plurality of separately controllable units of computing circuitry based on the compute kernel, wherein a portion of the logic that is generated to be performed by the plurality of separately controllable units of computing circuitry outside the performance-critical compute path is generated based at least in part on the reduced clock frequency.