Compute-in-Memory Circuit Using Global Bit-Line Convolution
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Solution Overview
Problem
Conventional computer systems face inefficiencies in performing complex tasks like machine learning due to high power consumption and poor performance in executing multiply-and-accumulate operations, which are not optimized for these tasks.
Innovation Solution
The implementation of a compute-memory circuit that uses standard data storage cells by performing computations on global bit lines instead of local bit lines, allowing for area-efficient and power-effective execution of multiply-and-accumulate operations through multiplier circuits and analog-to-digital converter circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional computer systems execute machine learning algorithms using processors or processor cores, then the system can perform complex tasks like language processing and image recognition, but power dissipation becomes excessive and performance becomes undesirable
Solution Approach 1:
The patent merges memory storage and computation functions into a single integrated structure. Weight values are stored in memory cells while multiplier circuits perform computations directly on stored data, eliminating the need to move data between separate memory and processor components. This combination enables multiply-and-accumulate operations to be performed within the memory array itself, dramatically reducing power consumption while improving performance for machine learning workloads
Solution Approach 2:
The patent introduces global bit lines as intermediary conduits that carry both stored weight values and activation signals to multiplier circuits. These global bit lines serve as the medium through which data flows from memory storage locations to computation units without requiring traditional data buses or intermediate registers, reducing the energy overhead associated with data transport
2Area of stationary object
If standard data storage cells are used in compute-memory circuits, then area efficiency is improved, but computation capability must be maintained
Solution Approach 1:
The patent makes standard data storage cells serve dual purposes: they function as both memory elements for storing weight values and as computational units when activated by multiplier circuits. The same physical storage cells that hold data can have their contents multiplied by activation signals and accumulated, allowing standard cells to perform both storage and computation functions without requiring specialized high-area components
Solution Approach 2:
The patent segments the computation process into discrete multiplier circuits that operate on individual weight values stored in memory cells. Each multiplier circuit handles a specific weight value and its corresponding activation signal, performing localized multiply-and-accumulate operations. This segmentation allows standard storage cells to be used throughout the array while computation is distributed across multiple simple multiplier units
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the area efficiency and reduces power consumption while maintaining performance, enabling more effective execution of machine learning algorithms by leveraging standard bit cells and optimizing computation within memory circuits.
Implementation Method 1
the multiplier circuits are configured to generate respective partial products, and modify the voltage level of the global bit line based on the partial products. By modifying the voltage level of the global bit line, the compute-memory circuit accumulates the partial products such that the resultant voltage of the global bit line corresponds to a product of first and second operands
Data Source
AI summary
A compute-memory circuit included in a computer system includes multiple data storage cells and multiplier circuits. The data storage cells store weight values associated with a first operand. The multiplier circuits are coupled to a global bit line and receive the weight values via local bit lines coupled to the data storage cells. Using the received weight values and activation signals indicative of a second operand, the multiplier circuits modify a voltage level of the global bit line. The resultant voltage level on the global bit line is indicative of a product of the first and second operands, and can be converted to a digital value using an analog-to-digital converter circuit.