Compute-in-Memory Cell Merging Logic Circuit to Reduce Chip Area
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Solution Overview
Problem
Current compute-in-memory (CIM) systems face inefficiencies in performing neural network computations due to the high computational intensity and large data sets, leading to increased time and energy consumption from transferring data between memory and processors, especially in deep learning applications like convolutional neural networks (CNNs).
Innovation Solution
The implementation of CIM devices with memory cells electrically connected to multiplication logic circuits that provide bitwise multiplication operations, reducing the number of transistors and read word lines compared to conventional configurations, allowing for efficient in-memory multiply operations across multiple rows of memory cells, such as two, three, or four rows, and supporting various memory cell types like SRAM, MRAM, and DRAM.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is transferred between memory and processor for computational steps, then computation can be performed, but time consumption and energy consumption increase
Solution Approach 1:
The patent merges the memory cell and multiplication logic circuit into a single integrated structure. The memory cell stores weights while the multiplication circuit performs computations directly on these stored values, eliminating the need to transfer data between separate memory and processor components. This integration enables compute-in-memory operations where storage and computation occur in the same physical location, directly resolving the time loss from data transfer.
2Quantity of substance
If conventional memory configurations are used, then memory storage is achieved, but the number of transistors and read word lines increases chip space occupation
Solution Approach 1:
The invention combines multiple functions (weight storage, multiplication, and read operations) into a single memory cell structure. By integrating the multiplication logic circuit directly with the memory cell, the design eliminates the need for separate read word lines and external multiplication circuits, thereby reducing the overall chip area required for a given memory storage capacity.
Solution Approach 2:
The memory cell is designed to perform multiple functions: storing weights, performing multiplication operations, and supporting read operations. This multi-functional design means that a single cell structure replaces what would traditionally require separate components, reducing the total number of transistors and read word lines needed on the chip.
3Productivity
If conventional memory configurations are used, then memory operations are performed, but energy consumption increases
Solution Approach 1:
By merging the multiplication logic circuit with the memory cell, the patent enables computations to be performed directly on stored data without transferring it to a separate processor. This eliminates the energy consumption associated with data movement between memory and processor, which is typically the dominant energy cost in conventional architectures.
Data Source
AI summary
A device includes a first memory cell, a second memory cell, a first logic element, a second logic element, and a third logic element. The first memory cell is configured to store a first bit at a first node, and the second memory cell is configured to store a second bit at a second node. The first logic element includes a first node input terminal coupled to the first node, the second logic element includes a second node input terminal coupled to the second node, and the third logic element includes a first input terminal coupled to a first output terminal of the first logic element and a second input terminal coupled to a second output terminal of the second logic element.