Compute-in-Memory Circuitry for FPGA Bandwidth and Latency Limits
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Solution Overview
Problem
Existing programmable logic devices face bandwidth and latency constraints when performing arithmetic computations that require large amounts of data stored off-chip, as these devices often rely on transferring data between separate memory and processing units.
Innovation Solution
The implementation of compute-in-memory circuitry within the memory sectors of a base die, allowing for arithmetic computations to take place where data is stored, thereby reducing the need for data transfer and mitigating bandwidth and latency constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If data is stored off-chip in separate memory units, then storage capacity is increased, but bandwidth and latency constraints worsen due to data transfer requirements
Solution Approach 1:
The patent merges memory storage and arithmetic computation functions into a single integrated circuit die. Memory sectors are combined with arithmetic logic units to perform computations directly where data is stored, eliminating the need for separate memory and processing units. This integration resolves the bandwidth and latency constraints by removing data transfer requirements between separate components.
Solution Approach 2:
The patent introduces an intermediary interface that enables direct communication between the programmable logic device and the integrated circuit die with compute-in-memory circuitry. This intermediary connection allows data to be accessed and processed without traditional data transfer bottlenecks, mitigating bandwidth and latency constraints while maintaining access to off-chip stored data.
2Device complexity
If data transfer between separate memory and processing units is used, then device complexity is reduced, but operational bottlenecks increase due to bandwidth and latency constraints
Solution Approach 1:
The patent combines memory storage and arithmetic computation capabilities within the same integrated circuit die. Memory sectors are directly integrated with arithmetic logic units, allowing data to be processed in-place without transfer to separate processing units. This merging eliminates operational bottlenecks while maintaining relatively simple device architecture through functional integration.
3Productivity
If compute-in-memory circuitry is implemented within memory sectors, then computation efficiency is improved, but device complexity increases
Solution Approach 1:
The patent integrates arithmetic logic units directly within memory sectors on the same integrated circuit die. This merging of computation and storage functions enables efficient compute-in-memory operations where data can be processed without external transfer. The complexity increase is managed through systematic integration, where the combined memory-computation units are organized in a structured manner that balances enhanced computation efficiency with controlled device complexity.
Data Source
AI summary
An integrated circuit device may include programmable logic circuitry on a first integrated circuit die and memory that includes compute-in-memory circuitry on a second die. The programmable logic circuitry may be programmed with a circuit design that operates on a first set of data. The compute-in-memory circuitry of the memory may perform an arithmetic operation using the first set of data from the programmable logic circuitry and a second set of data stored in the memory.