Reconfigurable Compute Memory With Embedded Logic Gates
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Solution Overview
Problem
Traditional computer architectures face significant delays due to high read and compute times, particularly in artificial-intelligence neural-network computations, which are exacerbated by the inefficiencies in performing parallel general matrix multiplication operations.
Innovation Solution
The integration of logic gates within a memory array, where each logic gate is coupled to pairs of memory cells, allowing for efficient performance of logical operations by reducing the need for separate read and compute steps through embedded logic functions within the memory architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If data are stored in separate memory and read before calculation, then data storage capacity is improved, but read time and compute time increase causing performance delays
Solution Approach 1:
The patent merges memory storage and logic computation into a single integrated structure. Logic gates are physically embedded within the memory array, allowing data to be stored and processed in the same location without requiring separate read and compute operations. This eliminates the time delay associated with transferring data between memory and processing units.
Solution Approach 2:
The patent introduces a new spatial dimension for computation by embedding logic gates vertically within the memory array structure. Instead of separate memory and processing units, the logic gates are positioned at specific locations within the memory array, enabling in-memory computation that occurs in the same physical space where data is stored.
2Device complexity
If traditional separate memory and processing units are used, then device simplicity is improved, but computing performance deteriorates due to substantial delays in read and compute operations
Solution Approach 1:
The patent combines memory storage and logic processing functions into a single hybrid structure. Logic gates are integrated directly within the memory array, creating an unified device that performs both storage and computation without requiring separate units and data transfer mechanisms.
3Loss of time
If logic gates are integrated within memory array, then read and compute time are reduced improving performance, but device complexity increases
Solution Approach 1:
The patent segments the memory array into distinct regions with specific functions. Memory cells are organized in rows and columns, with logic gates strategically positioned at specific locations within the array. This segmentation allows for systematic integration of computation capabilities while maintaining the underlying memory structure.
Solution Approach 2:
The patent applies local quality by placing specific logic gates at specific locations within the memory array based on computational requirements. Different regions of the memory array can be configured with different logic gate types (AND, OR, XOR, etc.) to optimize for specific computational tasks while maintaining overall system functionality.
Data Source
AI summary
A memory includes an array with rows and columns of memory cells. The rows include a first row and a second row. The memory also includes a plurality of logic gates in the array. Each logic gate of the plurality of logic gates includes a first input coupled to a respective memory cell in the first row, a second input coupled to a respective memory cell in the second row, and an output. The memory further includes a plurality of sense lines in the array. The output of each logic gate of the plurality of logic gates is coupled to a sense line of the plurality of sense lines.