Compute Slice Memory Dependence Prediction Using a Global Aliasing Table
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Solution Overview
Problem
Modern computing architectures face challenges in maintaining memory semantics across multiple processor cores due to increased computational parallelism, leading to potential memory access hazards and performance bottlenecks.
Innovation Solution
Implement a parallel architecture with compute slices and a global aliasing table (GAT) to predict memory dependencies, stall load instructions until previous store instructions complete, and use barrier registers for data communication between slices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If code execution parallelism is increased to improve processing capability, then productivity is improved, but memory access hazards and reliability deteriorate
Solution Approach 1:
A global aliasing table (GAT) is introduced as an intermediary data structure to track and manage memory aliasing information across multiple compute slices. The GAT stores load and store instruction addresses, enabling the system to detect potential memory hazards before they occur, thus maintaining reliability while allowing parallel execution to proceed.
Solution Approach 2:
The system performs preliminary analysis of memory access patterns by storing load and store instruction addresses in the GAT before parallel execution begins. This advance preparation enables the detection of potential aliasing hazards and allows the system to establish safe execution boundaries in advance, preventing memory access conflicts during parallel operation.
2Reliability
If memory dependence prediction is implemented to prevent hazards, then reliability is improved, but device complexity increases
Solution Approach 1:
The memory dependence prediction functionality is segmented into discrete, manageable components: compute slices that execute parallel code segments, a global aliasing table for tracking memory addresses, and hazard detection logic that operates independently on each load instruction. This segmentation allows the complex prediction mechanism to be implemented modularly without overwhelming system complexity.
Solution Approach 2:
The system uses address copying and comparison rather than complex analysis. Load and store instruction addresses are copied into the GAT and compared against existing entries to detect potential aliasing. This simple copying and matching approach provides reliable dependence prediction without requiring complex analytical mechanisms.
3Productivity
If speculative execution is used to increase throughput, then productivity is improved, but memory semantics and reliability worsen
Solution Approach 1:
The GAT provides feedback mechanisms that monitor memory access patterns during speculative execution. When a load instruction's address matches a stored store address in the GAT, the system receives feedback indicating a potential hazard, allowing it to adjust execution accordingly while maintaining the benefits of speculative execution for non-hazardous operations.
Data Source
AI summary
A processing unit is accessed that includes a plurality of compute slices, a control unit, and a global aliasing table (GAT). Each compute slice within the plurality of compute slices includes at least one execution unit, is known to a compiler, and is coupled to a successor compute slice and a predecessor compute slice. A first compute slice executes a load instruction. The load instruction is associated with a target address. The load instruction is predicted that it will alias with a previous store instruction. The previous store instruction executes on a previous compute slice among the plurality of compute slices. The predicting is based on the GAT. The load instruction is stalled until the previous store instruction completes execution on the previous compute slice. The load instruction is allowed to execute. The predicting includes searching, in the GAT, for an entry which includes the load instruction.