Compute Storage Tiles Dynamic Reconfiguration
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Solution Overview
Problem
Existing computer architectures face data access bottlenecks and energy wastage due to compartmentalized computational and storage structures, requiring inaccurate memory distribution assumptions that lead to excess memory allocation or time-consuming transfers.
Innovation Solution
A fine-grained distribution of memory structures among processing tiles, where each tile can be dynamically reconfigured to provide either memory or computational abilities, allowing for precise tailoring of memory to processors and facilitating close interaction between memory and computational structures without separate interconnection switches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If memory structures are closely integrated with processing structures, then data access speed is improved, but device complexity increases due to the need for dynamic reconfiguration capabilities
Solution Approach 1:
The patent implements dynamic reconfiguration of tiles between memory and processing modes through programmable interface circuits that can change the functional state of memory elements on-the-fly, allowing the system to adapt its architecture based on computational needs rather than being fixed in a static configuration
Solution Approach 2:
Each tile is designed with multi-functionality, containing both memory elements and processing elements that can be dynamically activated. The interface circuits enable the same physical tile to serve as either memory or processor depending on configuration, eliminating the need for separate dedicated memory and processing units
2Length of moving object
If memory is distributed among processors, then data transfer distance is reduced, but memory allocation efficiency deteriorates due to inaccurate assumptions about memory usage
Solution Approach 1:
The system dynamically adjusts memory allocation by reconfiguring tiles from processing mode to memory mode based on actual runtime memory requirements. This allows the architecture to adapt to varying memory demands of different processes without relying on static pre-allocation assumptions, optimizing both local memory availability and overall system memory efficiency
3Adaptability or versatility
If separate interconnection switches are used between memory and processing structures, then routing flexibility is improved, but device complexity and energy consumption increase
Solution Approach 1:
The patent merges the interconnection function directly into the tile structure itself. The interface circuits within each tile handle both memory access and processing operations, eliminating the need for separate interconnection switches. Data flow is managed through the tile's internal routing capabilities, reducing overall system complexity while maintaining flexibility
Solution Approach 2:
Each tile is self-sufficient with integrated interface circuits that manage its own memory access and processing operations without requiring external switching infrastructure. The tiles autonomously handle data routing between their memory and processing elements, reducing dependency on complex centralized interconnection networks
Data Source
AI summary
A computer architecture employs multiple intercommunicating tiles each holding an array of memory elements. Programmable decoding circuitry allows these memory elements to be used as local memories (including content addressable memories or random access memories), logic elements or interconnect elements. The ability to dynamically change the function of any of these tiles allows tight integration of memory and logic tailored to particular calculation problems reducing costs in data transfer.