Configurable Compute Unit FIFO Synchronization for Stable Data Flow
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Solution Overview
Problem
Existing solutions for managing data flow stability and synchronization in configurable integrated circuits are resource-intensive and inflexible, leading to suboptimal use of computational units and increased complexity in modifying data flows.
Innovation Solution
A computational unit with a buffer memory of first in, first out type (FIFO) is used to store input data and trigger operations based on validity signals, allowing for independent and asynchronous data processing, thereby ensuring data stability and synchronization without the need for time offsets or complex trigger instants.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a time offset is inserted between two successive computational units using a shift register, then data stability and synchronization are improved, but hardware resource consumption increases
Solution Approach 1:
A FIFO buffer is introduced as an intermediary component between computational units to manage data timing and synchronization. The FIFO buffer stores incoming data temporarily and releases it at the appropriate time, acting as a mediator that eliminates the need for complex shift registers while ensuring data stability and synchronization between computational units operating at different speeds or times.
2Reliability
If trigger instants are predetermined for each computational unit, then data synchronization is improved, but system complexity and difficulty of modification increase
Solution Approach 1:
The computational units are designed to autonomously manage their own data readiness and synchronization through local FIFO buffers and status flags. Each unit independently determines when its input data is ready and when it can proceed with computation, eliminating the need for a centralized orchestrator to predetermine and manage trigger instants for all units. This self-service approach reduces system complexity while maintaining synchronization.
Solution Approach 2:
A feedback mechanism using validity flags and status signals is implemented to communicate data readiness between computational units. When data is stored in a FIFO buffer, a validity flag is set to indicate readiness. Subsequent computational units monitor these flags to determine when to proceed with their operations, creating a decentralized feedback-based synchronization system that is simpler and more flexible than predetermined trigger instants.
3Manufacturing precision
If computational units wait for data stability before processing, then data accuracy is improved, but computational productivity decreases
Solution Approach 1:
Data is pre-processed and stored in FIFO buffers before being passed to computational units. The buffering action is performed in advance, allowing computational units to immediately process data as it becomes available without waiting for stability or synchronization. This preliminary action ensures data accuracy is maintained while eliminating wait times that would reduce computational productivity.
Data Source
AI summary
A computational unit of a configurable integrated circuit includes an input receiving data, an output and a core which is configured to execute an operation on the basis of at least one datum in order to obtain a result, and transmit the result to the output. The unit further includes a memory of first in, first out type associated with each input and configured to store each datum received by the input. The unit triggers the storage of a datum when a validity signal of a predefined value is detected, transmits, to the core, a stored datum and triggers an execution of the operation when a datum is stored in each memory and when no execution of the operation is in progress. The unit transmits, to the output, a validity signal of the predefined value at the same time as each transmitted result, and a different one otherwise.