Computer Bus Packet Error Handling with Header-First Processing
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Solution Overview
Problem
As data rates for serial links exceed 32.0 GT/s, maintaining a bit error rate (BER) of 10^-12 becomes challenging due to cross-talk, inter-symbol interference, and channel losses, especially in systems with multiple lanes, leading to correlated burst errors that conventional error correction mechanisms struggle to address effectively.
Innovation Solution
Implementing mechanisms and logic circuitry to log error locations, adjust Forward Error Correction (FEC) and Cyclic Redundancy Check (CRC) based on error correlation, and enable Low-Latency End Data Bad/Late Poison mode to pipeline packet processing without waiting for full packet receipt, using a common physical layer (PHY) to support multiple interconnect protocols like PCIe, CXL, and UPI.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional error correction mechanisms are used at data rates exceeding 32.0 GT/s, then error detection and correction capability is maintained, but correlated burst errors due to cross-talk and inter-symbol interference cannot be effectively addressed
Solution Approach 1:
The patent segments the error correction approach by implementing per-lane error correction independent of other lanes. Each lane processes and corrects errors autonomously, preventing correlated burst errors from affecting multiple lanes simultaneously. This is achieved through separate FEC encoders and decoders for each lane, with independent error correction logic that operates on individual lane data streams.
Solution Approach 2:
The patent applies preliminary action by performing Forward Error Correction encoding before transmission to proactively protect against correlated burst errors. The FEC encoder adds redundant data to each lane's signal in advance, enabling the receiver to correct errors without retransmission. This preliminary protection mechanism is established during link initialization and maintains error correction capability throughout operation.
2Reliability
If full packet receipt and verification is required before processing, then data integrity is ensured, but latency increases
Solution Approach 1:
The patent applies preliminary action by verifying the packet header before complete packet receipt to determine if the packet is valid. This allows the system to prepare for processing in advance and avoid waiting for the entire packet if the header indicates validity. The header verification includes checking error correction codes and routing information to preliminarily assess packet integrity.
Solution Approach 2:
The patent segments packet processing into header verification and body processing stages. The header is verified and processed separately from the packet body, allowing early determination of packet validity. This segmentation enables parallel processing where valid packets can be prepared for body processing while still being received, reducing overall latency while maintaining integrity through separate verification of critical header fields.
3Adaptability or versatility
If a common physical layer is used to support multiple interconnect protocols, then device versatility is improved, but protocol-specific optimization may be compromised
Solution Approach 1:
The patent implements universality by designing a common physical layer that supports multiple interconnect protocols including PCIe, CXL, and UPI. The physical layer uses a unified signal interface and basic transmission infrastructure that can operate with different protocol stacks. This common foundation provides versatility while allowing protocol-specific optimizations at higher layers through configurable parameters and protocol-aware processing in the link and transaction layers.
Solution Approach 2:
The patent applies dynamics by making the physical layer configurable and adaptable to different protocol requirements. The system can dynamically adjust parameters such as data rate, lane configuration, and error correction settings based on the active protocol. This dynamic configuration allows the common physical layer to optimize performance for each specific protocol while maintaining multi-protocol support through a single unified interface.
Data Source
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AI summary
Systems and devices can include protocol stack circuitry to perform certain methods, including receiving a flow control unit (flit) header and a transaction layer packet (TLP) payload, the TLP payload comprising a first portion and a second portion, determining that the flit header is free from errors, forwarding the flit header and the first portion of the TLP payload to a link partner based on the flit header being free from errors, identifying that the flit contains an error from the second portion of the TLP payload, and sending a data link layer packet (DLLP) to the link partner to indicate the error in the TLP payload.