Computer System Testing via Logical Partitioning to Reduce Interference

Solution Overview

Problem

Modern computer systems face challenges in maximizing power and temperature consumption across multiple components during testing, as interference between components reduces the measured stress and thermal response when multiple components are targeted concurrently, leading to inaccurate simulations of extreme operating conditions.

Innovation Solution

A method and system that analyze the computer system architecture to identify and prioritize power-consuming components, create instruction sets to stress these components, and alter them to minimize interference by partitioning resources and executing them on separate threads, thereby reducing access contention and maximizing concurrent stress.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple components are targeted concurrently during testing, then the testing efficiency is improved, but the measured power consumption and thermal response are reduced due to interference between components

Engineering Contradiction:

Improvetesting efficiencyVSAvoidmeasured power consumption

Core Design Contradiction:

ProductivityVSMeasurement precision

Solution Approach 1:

The patent segments the instruction sets to be executed on different logical partitions of the system. By dividing the system into separate logical partitions and assigning different instruction sets to each partition, the patent reduces interference between concurrent operations while maintaining testing efficiency. Each partition operates with dedicated resources, ensuring accurate measurement of power consumption and thermal response for targeted components.

Inventive Principle:

Principle #1Segmentation

2Productivity

If multiple components are targeted concurrently during testing, then the testing efficiency is improved, but the measured thermal response is reduced due to interference between components

Engineering Contradiction:

Improvetesting efficiencyVSAvoidmeasured thermal response

Core Design Contradiction:

ProductivityVSTemperature

Solution Approach 1:

The patent segments the instruction sets to be executed on different logical partitions of the system. By dividing the system into separate logical partitions and assigning different instruction sets to each partition, the patent reduces interference between concurrent operations while maintaining testing efficiency. Each partition operates with dedicated resources, ensuring accurate measurement of power consumption and thermal response for targeted components.

Inventive Principle:

Principle #1Segmentation

3Adaptability or versatility

If algorithms stress both memory and cache concurrently, then the testing coverage is improved, but the access bandwidth to individual components is reduced

Engineering Contradiction:

Improvetesting coverageVSAvoidaccess bandwidth

Core Design Contradiction:

Adaptability or versatilityVSSpeed

Solution Approach 1:

The patent segments the instruction sets to be executed on different logical partitions of the system. By dividing the system into separate logical partitions and assigning different instruction sets to each partition, the patent reduces interference between concurrent operations while maintaining testing efficiency. Each partition operates with dedicated resources, ensuring accurate measurement of power consumption and thermal response for targeted components.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a new dimension of execution by utilizing multiple logical partitions simultaneously. Instead of sequentially executing stress tests or allowing them to interfere in a single execution context, the patent creates parallel execution paths through logical partitioning, effectively adding a dimensional layer to the testing architecture that allows comprehensive coverage without resource contention.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS8402292B2Method and apparatus to maximize power of a computer system for effective testing

Publication Date: 2013.03.19 ORACLE AMERICAN INC

AI summary

Implementations of the present invention may involve methods and systems to improve the combined power consumption and thermal response of individual components of a computer system as the components are stressed concurrently during simulation or testing of the system. A group of operating system-level instruction sets for several individual components of the computer system may be designed to stress the components and executed concurrently while power and thermal measurements are taken. The instruction sets may utilize one or more software threads of the computer system or hardware threads such that minimal interference between components occurs as the system is tested. Further, the system components may be partitioned between separate instruction sets. By minimizing the interference between the components while the system is operating, a more accurate power consumption and thermal effect measurements may be taken on the computer system to better approximate the performance of the system.