Computing Chip Layout Using Segmented Columns for Space Utilization
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Solution Overview
Problem
Existing computing chips have inefficient space utilization due to incomplete columns of cell points, leading to a less compact layout and increased occupied space.
Innovation Solution
The computing chip is designed with a pipeline configuration that includes a combination of first and second combinational logic circuits and registers, where cell points are optimally arranged to occupy equal areas, allowing for flexible distribution and sharing of cell points across columns, thereby maximizing space utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If circuits or devices are designed to occupy rectangular areas composed of rows and columns of cell points, then the layout is regular and easy to manufacture, but space utilization is inefficient and the chip occupies more area
Solution Approach 1:
The patent divides the chip layout into complete columns and incomplete columns, with each column containing multiple rows of cell points. By segmenting the layout this way, circuits can be arranged to fully utilize complete columns while efficiently filling incomplete columns, reducing wasted space at the edges.
Solution Approach 2:
The patent introduces a column-based dimensional organization where cell points are arranged in multiple rows within each column. This dimensional approach allows circuits to be distributed across rows and columns, enabling better space utilization by filling gaps that would otherwise be wasted in traditional rectangular block layouts.
2Device complexity
If cell points are arranged in traditional rectangular blocks, then the design is simple, but the layout is not compact and space is not fully utilized
Solution Approach 1:
The patent segments the chip area into complete columns and incomplete columns, each containing multiple rows of cell points. This segmentation allows for a systematic approach to filling space, where complete columns are fully utilized and incomplete columns are efficiently packed with remaining circuit elements, achieving compact layout without excessive design complexity.
Solution Approach 2:
The patent applies different layout strategies to different regions: complete columns are filled completely with circuits, while incomplete columns are strategically filled to maximize space utilization. This local quality approach allows the layout to be optimized in each region according to its specific characteristics, achieving overall compactness.
Data Source
AI summary
This disclosure relates to a computing chip, a hashrate board, and a data processing apparatus. The computing chip includes a plurality of operation stages arranged in a pipeline configuration. Each operation stage includes: a first combinational logic circuit occupying a plurality of first cell points adjacent to each other, at least a portion of the first cell points being located in a first incomplete column; one or more second combinational logic circuits each occupying one or more second cell points, at least a portion of the second cell points being located in a second incomplete column; and a plurality of registers each occupying a plurality of third cell points, at least a portion of the third cell points being located in the first incomplete column or the second incomplete column. The first cell points, the second cell points, and third cell points occupy equal areas on the computing chip.