3D Stacked Computing-In-Memory Chip Architecture
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Solution Overview
Problem
The von Neumann architecture's separation of processor and memory leads to data transfer latency and power consumption issues, limiting the computing power of processors and overall system performance.
Innovation Solution
A computing-in-memory system architecture that integrates arrays of computing-in-memory cells on multiple overlapping chips, along with a peripheral analog circuit IP core and digital circuit IP core on a separate chip, communicatively coupled via an interface module.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is frequently transferred between processor and memory in von Neumann architecture, then computing operations can be performed, but data transfer latency increases and operating speed decreases
Solution Approach 1:
The patent combines memory and computing units into a single computing-in-memory chip, allowing data to be processed in-place without frequent transfers to separate processor memory interfaces, thereby reducing transfer latency and improving operating speed
Solution Approach 2:
The patent transitions from traditional 2D memory arrays to 3D stacked memory-in-memory architectures with multiple layers, enabling parallel processing operations across different memory layers and reducing data access latency through vertical stacking
2Ease of manufacture
If separate chips are used for memory and processor, then manufacturing processes are simplified, but data transfer power consumption increases
Solution Approach 1:
The patent merges memory cells and computing units onto the same chip substrate, eliminating the need for high-speed external data buses and significantly reducing power consumption associated with data transfer between separate processor and memory chips
Solution Approach 2:
The patent divides the computing-in-memory chip into multiple functional blocks including memory arrays, computing units, and control logic that can be manufactured using separate process steps and then integrated, maintaining manufacturing simplicity while enabling low-power in-memory computing
3Loss of time
If computing units are integrated with memory on the same chip, then data transfer latency is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the computing-in-memory chip into distinct memory array regions and computing unit regions that can be manufactured using different process optimizations, allowing standard CMOS processes to handle memory cells while specialized processes handle analog computing units, thereby managing manufacturing precision requirements
Solution Approach 2:
The patent introduces control logic and interface circuits as intermediary components between memory arrays and computing units, providing buffering and synchronization that tolerates manufacturing variations and ensures reliable operation despite precision limitations
4Productivity
If multiple chips are stacked to increase computing capacity, then system performance improves, but device complexity increases
Solution Approach 1:
The patent implements a stacked architecture where multiple computing-in-memory chips are vertically stacked with through-silicon vias and interconnect layers, nesting multiple processing layers within a compact footprint to increase computing capacity while managing complexity through standardized stacking interfaces
Data Source
AI summary
A computing-in-memory system, a packaging method for a computing-in-memory system, and an apparatus are provided. The computing-in-memory system includes: a plurality of first chips each integrated with one or more arrays of computing-in-memory cells of a computing-in-memory system, and arranged to overlap each other, where the one or more arrays of computing-in-memory cells are configured to perform computations on received data; a second chip integrated with a peripheral analog circuit IP core and a digital circuit IP core of the computing-in-memory system; and an interface module configured to communicatively couple the second chip to each first chip.