Computing-in-Memory Chip Architecture for Latency Reduction
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Solution Overview
Problem
In computing systems with von Neumann architecture, the speed mismatch between processor operations and memory transfers limits computing power, especially when large numbers of computing-in-memory chips are involved, leading to increased data transfer latency and power consumption.
Innovation Solution
A computing-in-memory system architecture that integrates arrays of computing-in-memory cells, a peripheral analog circuit IP core, a digital circuit IP core, and a NAND memory on separate chips, with an interface module for high-speed data transfer, allowing the chips to access data stored in the NAND memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is frequently transferred between processor and memory in von Neumann architecture, then instructions can be executed, but data transfer latency increases and computing speed decreases
Solution Approach 1:
The patent merges memory and computing functions into a single integrated structure where memory cells directly perform computational operations. The memory array includes computing units that can execute calculations on stored data without requiring transfer to a separate processor, thereby eliminating data transfer latency and improving computing speed simultaneously.
2Productivity
If computing-in-memory chips are used to improve computing speed, then data transfer limitations are reduced, but device complexity increases
Solution Approach 1:
The computing-in-memory system is divided into multiple independent chips, each containing a portion of the memory array and associated computing units. This segmentation allows for modular design, easier manufacturing, and scalable system configuration while maintaining the integrated memory-computing functionality that improves computing speed.
Data Source
AI summary
A computing-in-memory system, a packaging method for a computing-in-memory system, and an apparatus are provided. The computing-in-memory system includes: one or more first chips each integrated with one or more arrays of computing-in-memory cells of a computing-in-memory chip, where the one or more arrays of computing-in-memory cells are configured to perform computations on received data; a second chip integrated with a peripheral analog circuit IP core and a digital circuit IP core of the computing-in-memory system; a third chip between the one or more first chips and the second chip, the third chip including NAND memory; and an interface module configured to communicatively couple the one or more first chips, the second chip, and the third chip, such that the one or more first chips and the second chip have access to data stored in the NAND memory.