Computing-in-Memory Chip Layout for Reduced Data Transfer Bottlenecks
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Solution Overview
Problem
The von Neumann architecture's separation of memory and processor leads to inefficient data transfer, limiting processor computing power and overall system performance due to mismatched memory and processor speeds.
Innovation Solution
A computing-in-memory chip architecture is introduced, where arrays of computing-in-memory cells are integrated on one side of the chip and peripheral analog and digital circuit IP cores are integrated on the opposite side, with an interface module for communication between the two.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If memory and processor are separated as in von Neumann architecture, then functional modularity is improved, but data transfer efficiency deteriorates due to speed mismatch between memory and processor
Solution Approach 1:
The patent merges the memory array and processing circuits into a single integrated computing-in-memory chip. The memory cells are directly coupled with compute circuits that can perform computational operations on data stored in the memory cells without requiring data to be transferred to a separate processor, thereby eliminating the speed mismatch problem while maintaining functional integration.
Solution Approach 2:
The patent introduces a new architectural dimension by placing processing circuits at the edge of the memory array rather than separating them completely. The compute circuits are positioned to directly access memory cells through shared bit lines and word lines, creating a spatial relationship that enables in-situ computing while preserving the modular benefits of separate functional blocks.
2Ease of manufacture
If computing-in-memory cells are integrated on one side and peripheral circuits on the other side of the chip, then chip utilization is improved, but inter-subchip communication complexity increases
Solution Approach 1:
The patent segments the computing-in-memory chip into two sub-chips: a first sub-chip containing the memory array and a second sub-chip containing peripheral analog and digital circuit IP cores. These sub-chips are integrated on opposite sides of the chip substrate and communicatively coupled through an interface module, allowing each sub-chip to be optimized for its specific function while maintaining overall system integration.
Solution Approach 2:
The patent introduces an interface module as an intermediary between the first sub-chip (memory array) and the second sub-chip (peripheral circuits). This interface module facilitates efficient communication and data transfer between the two sub-chips, managing the complexity of inter-subchip interactions while enabling the benefits of spatial separation and specialized integration.
Data Source
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AI summary
The present disclosure relates to a computing-in-memory chip architecture, a packaging method for a computing-in-memory chip, and an apparatus. The computing-in-memory chip architecture includes: one or more first sub-chips integrated on a first side of a computing-in-memory chip and integrated with one or more arrays of computing-in-memory cells of the computing-in-memory chip, where the one or more arrays of computing-in-memory cells are used to compute the received data; a second sub-chip integrated on a second side, opposite to the first side, of the computing-in-memory chip and integrated with a peripheral analog circuit IP core and a digital circuit IP core of the computing-in-memory chip; and an interface module configured to communicatively couple the second sub-chip to each of the one or more first sub-chips.