Computing-in-Memory Chip Shared ADC DAC Architecture
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Solution Overview
Problem
The existing computing-in-memory chip architecture requires multiple memory cell arrays with corresponding peripheral circuits, leading to a large circuit area and high cost, which hinders integration and cost-effectiveness.
Innovation Solution
The computing-in-memory chip employs a memory cell array structure where each memory cell sub-array is controlled by a local word line, allowing all sub-arrays in a row to share digital-to-analog converters (DACs) and analog-to-digital converters (ADCs), reducing circuit area and cost by activating or deactivating switch units based on the local word line control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple memory cell arrays are provided to meet complex operation requirements, then operational capability is improved, but circuit area and cost increase significantly
Solution Approach 1:
Multiple memory cell arrays are merged into a single shared array structure, with different sub-regions performing different operations through selective activation. The DAC and ADC are shared across all sub-arrays, eliminating redundant peripheral circuits while maintaining the capability to perform multiple operations through time-division and parallel activation control.
Solution Approach 2:
A single memory cell array is designed to perform multiple operational tasks by dividing it into multiple sub-arrays, each capable of different analog vector-matrix multiplication operations. The same physical hardware (memory cells, DAC, ADC) serves universal purposes for different computational functions through configurable activation patterns.
2Reliability
If each memory cell array is equipped with dedicated peripheral circuits including ADC and DAC, then operational independence is improved, but cost and area increase
Solution Approach 1:
The DAC and ADC peripheral circuits are merged into shared resources that serve multiple memory cell sub-arrays. Instead of having dedicated ADC/DAC for each sub-array, a single DAC converts digital input signals for all sub-arrays, and a single ADC converts analog output results from all sub-arrays, dramatically reducing the number of peripheral components while maintaining operational capability.
Solution Approach 2:
The system uses dynamic control mechanisms (local word lines and switch units) to activate specific sub-arrays as needed, providing operational independence through software/control logic rather than dedicated hardware. This allows the same physical circuit to serve multiple functions at different times, reducing hardware redundancy.
3Area of stationary object
If peripheral circuit area is reduced by sharing ADC and DAC, then integration and cost are improved, but control complexity increases
Solution Approach 1:
The memory cell array is segmented into multiple independent sub-arrays, each with its own local word line and switch units. This segmentation allows selective activation of individual sub-arrays without affecting others, simplifying the control logic compared to managing a single large array. Each sub-array can be independently controlled and activated based on computational requirements.
Solution Approach 2:
Local word lines act as intermediary control signals between the main control logic and individual sub-arrays. These local word lines, combined with switch units, provide a hierarchical control mechanism that manages the shared ADC/DAC resources efficiently, reducing the complexity at the top control level while maintaining fine-grained control capability.
Data Source
AI summary
In a computing-in-memory chip and a memory cell array structure, a memory cell array therein includes a plurality of memory cell sub-arrays arranged in an array. Each memory cell sub-array comprises a plurality of switch units and a plurality of memory cells arranged in an array; and first terminals of all memory cells in each column are connected to a source line, second terminals of all the memory cells are connected to a bit line, third terminals of all memory cells in each row are connected to a word line through a switch unit, a plurality of rows of memory cells are correspondingly connected to a plurality of switch units, control terminals of the plurality of switch units are connected to a local word line of the memory cell sub-array, and whether to activate the memory cell sub-array is controlled by controlling the local word line.