Computing In Memory Micro-Unit Logic Elements Matrix
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Solution Overview
Problem
The Von Neumann computer architecture is inefficient as data set sizes increase, leading to prolonged data transfer times between the central processing unit and memory, resulting in idle processor time due to slow transfer speeds.
Innovation Solution
Implementing a computing in memory model that uses dataflow models with programmable hardware, allowing for dynamic deployment of instruction set architecture, code, and routing instructions within computing in memory units, utilizing physical memory matrices and logic elements to process packets that carry instructions, data, and routing information, thereby reducing the need for external memory access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If data is stored in external memory and processed by central processing unit, then data storage capacity is improved, but data transfer time increases and processor idle time increases
Solution Approach 1:
The patent combines memory storage and processing functions into a single integrated structure. Memory cells are equipped with logic elements that can perform computations directly on stored data, eliminating the need for separate data transfer between external memory and processing units. This merging of storage and computation resolves the contradiction by allowing large data capacity while minimizing transfer time.
Solution Approach 2:
The patent divides the processing function into distributed logic elements embedded within memory cells. Each memory cell contains its own processing capability, allowing parallel processing of multiple data elements simultaneously. This segmentation enables the system to handle large datasets without sequential transfer delays.
2Quantity of substance
If data is stored in external memory and processed by central processing unit, then data storage capacity is improved, but processor idle time increases
Solution Approach 1:
By merging memory and processing units into an integrated memory structure, the patent eliminates the idle time that occurs when processors wait for data transfer. Processing can occur immediately on data as it is accessed within the memory array, maintaining continuous processor utilization while supporting large storage capacity.
Solution Approach 2:
The integrated memory structure enables continuous processing operations without interruption for data transfer. Multiple logic elements can process different data elements simultaneously in parallel, ensuring that processing activity remains continuous and productive while maintaining large data storage capability.
3Speed
If computing in memory units are implemented with programmable hardware, then processing speed is improved, but device complexity increases
Solution Approach 1:
The patent implements dynamically reconfigurable logic elements within memory cells that can be programmed to perform different computational functions. This dynamic capability allows the same hardware structure to adapt to various processing needs, achieving high processing speeds for different applications without requiring multiple specialized structures, thus managing complexity through reconfigurability rather than static specialization.
Data Source
AI summary
A method of computing in memory, the method including inputting a packet including data into a computing memory unit having a control unit, loading the data into at least one computing in memory micro-unit, processing the data in the computing in memory micro-unit, and outputting the processed data. Also, a computing in memory system including a computing in memory unit having a control unit, wherein the computing in memory unit is configured to receive a packet having data and a computing in memory micro-unit disposed in the computing in memory unit, the computing in memory micro-unit having at least one of a memory matrix and a logic elements matrix.