Computing Unit Safe Mode Using Instruction Check Values

The patent uses a single processor core that periodically copies its own state and executes instructions in a locked-step manner, rather than requiring two physical cores. This virtual duplication achieves the safety checking functionality while using only one physical core, thereby reducing power consumption while maintaining ASIL-D safety integrity level.

The single processor core performs multiple functions: it executes normal instructions, generates check values, and performs safety verification all within the same hardware unit. This multi-functionality eliminates the need for separate redundant cores, reducing overall power consumption while maintaining safety requirements.

Instead of duplicating the entire processor core hardware, the patent implements a virtual copying mechanism where a single core periodically creates and verifies copies of its execution state. This approach achieves safety redundancy through software/state copying rather than hardware duplication, significantly reducing chip area while maintaining ASIL-D compliance.

The safety verification functionality is nested within the single processor core's existing structure. The core embeds check value generation and verification logic within its normal instruction execution pipeline, rather than adding separate safety subsystems. This nesting approach minimizes additional chip area while achieving functional safety.

The patent implements a dynamic safety verification approach where the single core adaptively manages its own safety checking based on execution state. The core can dynamically switch between normal execution and safety verification modes, and the verification frequency can be adjusted based on performance requirements. This dynamic approach allows high-performance cores to maintain scalability while achieving functional safety.

The processor core performs its own safety verification without requiring external safety subsystems or additional cores. The core generates its own check values, performs self-verification, and manages its own safety state. This self-service capability makes the approach highly scalable and adaptable to different high-performance core architectures without requiring proportional increases in safety infrastructure.

The patent implements a feedback mechanism where the processor core continuously generates check values from executed instructions and compares them against expected values. This feedback loop provides continuous monitoring of instruction integrity, enabling detection of corruption in conventional memory systems. The check value comparison provides real-time feedback on memory reliability without requiring specialized safe memory hardware.

The patent replaces physical/m hardware-based safety mechanisms (such as specialized safe memory or redundant cores) with a software-based check value verification system. By using algorithmic check value calculation and comparison, the system achieves corruption detection capability in conventional memory without requiring specialized memory hardware, thereby reducing manufacturing cost while maintaining detection capability.