Adaptive Concatenated ECC for Varying Flash Cell Error Rates

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Solution Overview

Problem

Existing error correction codes (ECCs) in flash memory devices provide uniform protection for all bits, which is sub-optimal and leads to performance loss due to varying error probabilities among memory cells.

Innovation Solution

Adaptive Generalized Concatenated Codes (A-GCC) are introduced, providing different protection levels for different parts of the code word without requiring additional power or multiple code words, using constituent codes like polar codes and Reed-Solomon codes tailored to varying channel qualities.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If uniform error protection is applied to all bits using traditional GCC codes, then implementation simplicity is maintained, but error correction performance deteriorates due to varying error probabilities among memory cells

Engineering Contradiction:
Improveerror correction performanceVSAvoidcode structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies local quality by differentiating error protection levels for different portions of code words based on their error probabilities. Specifically, it divides code words into first code words and second code words, applying first error protection and second error protection respectively, where the protection levels are adapted to the local error characteristics of each portion rather than applying uniform protection across all bits.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent segments the code word structure into distinct portions (first code words and second code words) that can be protected by different error correction mechanisms. This segmentation allows the system to apply appropriate protection strategies to different segments based on their error characteristics, improving overall error correction performance while managing complexity through structured division.

Inventive Principle:
Principle #1Segmentation

2Reliability

If different protection levels are applied to different code words, then error correction efficiency is improved, but power consumption increases

Engineering Contradiction:
Improveerror correction efficiencyVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent changes the protection parameter selectively rather than uniformly. It applies different error protection levels (first error protection and second error protection) to different code words based on their error probabilities, thereby optimizing error correction efficiency while avoiding the power consumption penalty of applying maximum protection to all code words.

Inventive Principle:
Principle #35Parameter changes

3Adaptability or versatility

If multiple code words are used to provide varying protection, then adaptability to different channel qualities is improved, but device complexity increases

Engineering Contradiction:
Improveadaptability to channel qualityVSAvoidcode word management complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent introduces dynamics by making the protection level adaptive rather than static. The system dynamically selects between first error protection and second error protection for different code words based on their error probabilities, enabling adaptability to varying channel qualities while managing complexity through a structured, rule-based selection process rather than requiring complex real-time adjustments.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentEP4660810A1Adaptive generalized concatenated codes for low power ECC with varying overhead
Publication Date: 2025.12.10 SAMSUNG ELECTRONICS CO LTD
  • EP4660810A1 patent drawingFigure 1
  • EP4660810A1 patent drawingFigure 2A
  • EP4660810A1 patent drawingFigure 2B

AI summary

Methods, devices, and systems for controlling a storage system, including: a storage device configured to store a plurality of code words; and at least one processor configured to: obtain information bits; encode the information bits using a first code to obtain a first plurality of code words; encode the first plurality of code words using a second code to generate a second plurality of code words; update the first plurality of code words based on the second plurality of code words to generate an adaptive generalized concatenated code (A-GCC) code word; and store the A-GCC code word in the storage device, wherein each code word of the first plurality of code words is encoded using a different error protection level.