Concatenated Error Correction for Asymmetric Flash Memory Errors
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Solution Overview
Problem
Conventional error correction techniques in non-volatile memory, such as flash memory, are inadequate for correcting asymmetric errors due to their limited capability in addressing one-directional errors, which are common in programming operations, leading to inefficiencies in data integrity.
Innovation Solution
A system and method for concatenated error correction that involves an outer encoder generating a code word, dividing it into logical cells, computing parities, generating and inserting error correction bits, and performing asymmetric error correction to correct data bits, followed by symmetric error correction for residual errors, effectively addressing one-directional errors in non-volatile memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional asymmetric error correction code is used, then one-directional errors can be corrected, but errors in the opposite direction cannot be corrected
Solution Approach 1:
The error correction system is segmented into two distinct components: an asymmetric error correction code (AECC) for correcting one-directional errors and a symmetric error correction code (SECC) for correcting errors in both directions. This segmentation allows each code to specialize in specific error types, thereby resolving the contradiction between correcting one-directional errors and covering all error types.
Solution Approach 2:
The patent employs a composite error correction approach by combining AECC and SECC into a concatenated code structure. The AECC layer handles asymmetric errors first, and the SECC layer handles remaining symmetric errors. This composite structure provides comprehensive error correction coverage while maintaining the specialized advantages of each code type.
2Reliability
If more redundant bits are added for error correction, then error detection and correction capability improves, but storage efficiency decreases
Solution Approach 1:
The system applies partial error correction by using AECC to correct the most common asymmetric errors first, then applying SECC only for remaining symmetric errors. This partial approach corrects errors more efficiently than comprehensive correction methods, reducing the total redundant bits needed while maintaining high data integrity.
Solution Approach 2:
The patent changes the error correction parameters by selecting specific code rates and code lengths for AECC and SECC based on the expected error distribution in flash memory. By optimizing these parameters, the system achieves adequate error correction with minimal redundant bits, balancing reliability and storage capacity.
3Measurement precision
If complex error correction algorithms are used, then error correction accuracy improves, but processing complexity increases
Solution Approach 1:
The complex error correction task is segmented into two simpler sub-tasks: asymmetric error correction using AECC and symmetric error correction using SECC. Each segment uses a specialized, relatively simple algorithm optimized for its specific error type, reducing overall processing complexity while maintaining high detection accuracy.
Solution Approach 2:
The AECC acts as an intermediary layer between the raw data and the SECC processing. It first corrects asymmetric errors and passes the corrected (or partially corrected) data to the SECC layer. This intermediary approach simplifies the overall processing by breaking down the complex error correction task into manageable stages.
Data Source
AI summary
A system and method is provided for performing concatenated error correction. In one implementation, an apparatus for encoding data includes an outer encoder to generate a code word corresponding to received input data and a parity circuit to compute parities of logical cells of data, the logical cells of data being obtained from the code word and having a first logical cell. The apparatus also includes an inner encoder to generate an error correction bit for the first logical cell based on a first parity corresponding to the first logical cell, and to insert the error correction bit in the first logical cell.