Fan-Out Wafer Level Packaging with Concave Encapsulant Surface
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Solution Overview
Problem
Conventional fan-out wafer level packaging technologies face reliability concerns due to delamination issues in the dielectric layer, leading to I/O pad breakages and reduced processing yield.
Innovation Solution
A chip package structure and manufacturing method that involves a concave encapsulant surface dented toward the back surface, a first dielectric layer with acute-angle slanted openings exposing pads, and a patterned circuit layer formed on the dielectric layer to enhance bonding strength and improve step coverage during PVD processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional planar encapsulant surface is used in fan-out wafer level packaging, then the manufacturing process is simple, but delamination occurs between the dielectric layer and encapsulant, causing I/O pad breakages and reduced reliability
Solution Approach 1:
The patent applies curvature by forming a concave surface on the encapsulant instead of using a planar surface. The concave surface is created by dicing the encapsulated wafer at an angle or by selective removal of encapsulant material, resulting in a curved interface that increases the contact area between the encapsulant and dielectric layer, thereby preventing delamination and improving bonding strength.
Solution Approach 2:
The patent transitions from a two-dimensional planar interface to a three-dimensional concave surface by introducing curvature in the vertical dimension. This dimensional change allows the dielectric layer to conform to the curved encapsulant surface, creating a larger contact area and more robust mechanical interlocking that prevents delamination during subsequent processing and operation.
2Manufacturing precision
If vertical openings are formed in the dielectric layer, then the fabrication process is simple, but the patterned circuit layer cannot be uniformly formed and step coverage is poor
Solution Approach 1:
The patent applies asymmetry by forming openings with slanted side surfaces instead of vertical walls. The openings have asymmetric geometry where one side is angled relative to the substrate, which allows deposition materials to uniformly coat all surfaces including the bottom and slanted walls. This asymmetric opening geometry ensures complete step coverage for the patterned circuit layer while maintaining fabrication simplicity.
3Reliability
If chips are mounted with normal die bond force, then the mounting process is standard, but the adhesive layer does not provide sufficient contact area for encapsulant bonding
Solution Approach 1:
The patent applies preliminary action by first mounting the chips on the carrier with adhesive layer, then forming the encapsulant material over the entire assembly including the adhesive layer. This sequence allows the encapsulant to conform to and bond with the adhesive layer that is already in place, creating a larger contact area and more robust mechanical interlocking without requiring excessive mounting force.
Data Source
AI summary
A manufacturing method of a chip package structure includes: dicing a wafer to separate chips formed thereon; mounting the chips on a carrier, wherein an active surface and pads of each chip are buried in an adhesive layer disposed on the carrier, and a top surface of the adhesive layer between the chips is bulged away from the carrier; forming an encapsulant to encapsulate the chips and cover the adhesive layer, wherein the encapsulant has a concave surface covering the top surface of the adhesive layer and a back surface opposite to the concave surface; removing the carrier and the adhesive layer; forming a first dielectric layer to cover the concave surface and the active surface; forming a patterned circuit layer on the first dielectric layer, to electrically connect to the pads through openings in the first dielectric layer; and forming a second dielectric layer on the patterned circuit layer.