Concave Gate Dielectric for HVMOS Integration
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Solution Overview
Problem
The integration of High-Voltage Metal-Oxide-Semiconductor (HVMOS) devices with other semiconductor devices in fabrication is challenging due to their different structures and dimensions, particularly because the thicker gate dielectric required for HVMOS devices is not compatible with thinner gate dielectrics used in other devices, complicating manufacturing and increasing production costs.
Innovation Solution
A semiconductor device is manufactured with a gate dielectric having a concave profile, allowing the gate electrode to be formed lower than the substrate surface, enabling the integration of HVMOS devices with other devices like logic MOS devices by sharing the same inter-layer dielectric thickness, thus simplifying manufacturing and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If HVMOS devices use thicker gate dielectric to sustain high voltages, then voltage-sustaining capability is improved, but compatibility with other semiconductor devices using thinner gate dielectric deteriorates
Solution Approach 1:
The gate dielectric thickness is made non-uniform across the semiconductor substrate. HVMOS device regions receive thicker gate dielectric for voltage sustainment, while logic device regions receive thinner gate dielectric for optimal performance. This local differentiation resolves the contradiction by allowing each device type to have its specific dielectric thickness requirement met simultaneously.
Solution Approach 2:
The semiconductor substrate is divided into distinct regions (HVMOS device regions and logic device regions) with different gate dielectric thicknesses. This segmentation allows independent optimization of gate dielectric thickness for each device type, enabling HVMOS devices to sustain high voltages while logic devices maintain compatibility with standard thin dielectric processes.
2Adaptability or versatility
If HVMOS devices are integrated with other semiconductor devices, then device functionality is improved, but manufacturing complexity increases
Solution Approach 1:
Gate dielectric regions of different thicknesses are formed at different stages during the manufacturing process. Thicker gate dielectric for HVMOS devices is formed first, followed by thinner gate dielectric for logic devices in subsequent processing steps. This preliminary action sequence simplifies integration by establishing the thickness hierarchy early in manufacturing rather than requiring complex post-processing adjustments.
Solution Approach 2:
Different gate dielectric thicknesses are applied to different spatial regions of the substrate corresponding to different device types. This local quality approach allows HVMOS and logic devices to coexist on the same substrate with their respective dielectric requirements met, achieving integration without requiring entirely separate manufacturing lines.
3Reliability
If different gate dielectric thicknesses are used for different device regions, then device performance optimization is improved, but production cost increases
Solution Approach 1:
The manufacturing process is structured to form thicker gate dielectric in HVMOS regions during earlier processing steps, before thinner gate dielectric is deposited over the entire substrate in subsequent steps. This preliminary action approach utilizes the natural layering capability of deposition processes, avoiding the need for expensive selective deposition equipment or multiple separate fabrication lines.
Solution Approach 2:
A single gate dielectric deposition process serves multiple functions: it forms the thicker dielectric for HVMOS devices in some regions and the thinner dielectric for logic devices in other regions. This multi-functionality is achieved through a combination of preliminary thick dielectric formation followed by a universal thin dielectric deposition step that covers the entire substrate, reducing the need for device-specific processing equipment.
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, a gate dielectric, a gate electrode, and a pair of source/drain regions. The gate dielectric is disposed in the semiconductor substrate having an upper boundary lower than an upper surface of the semiconductor substrate, and an upper surface flush with the upper surface of the semiconductor substrate. The gate electrode is disposed over the gate dielectric having a first section over the upper boundary of the gate dielectric and a second section over the upper surface of the gate dielectric. The second section partially covers and partially exposes the upper surface of the gate dielectric. The pair of source/drain regions are disposed on opposing sides of the gate dielectric.