FinFET Gate Line Concave Cross-Section for Fine Pitch Reliability
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Solution Overview
Problem
The challenge in semiconductor manufacturing is forming reliable gate lines with fine pitches, as current techniques face limitations in reducing pattern sizes and maintaining device reliability with increasingly tight design rules.
Innovation Solution
A semiconductor device design featuring a gate line with a concave central portion and irregular shape, including a first and second gate electrode layer, where the second gate electrode layer protrudes from the first, and a barrier layer between the gate electrode layers and spacer layers, along with a gate insulating layer extending between the active region and spacer layers, to achieve a narrow width and reduced pitch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional gate line formation techniques are used, then manufacturing process is simple, but gate line reliability deteriorates with fine pitch
Solution Approach 1:
The gate line cross-sectional shape is changed from a conventional flat or convex shape to a concave shape, introducing a dimensional change in the vertical profile. This concave configuration modifies the stress distribution and electrical field characteristics, thereby improving gate line reliability at fine pitches without compromising manufacturability
Solution Approach 2:
The gate line structure is made non-uniform by introducing a concave region in the central portion while maintaining different characteristics at the central and lateral regions. This local variation in cross-sectional shape allows the gate line to exhibit improved reliability properties specifically where needed, while maintaining overall structural integrity
2Productivity
If device pitch is reduced to increase integration, then device density improves, but pattern formation reliability deteriorates
Solution Approach 1:
By modifying the gate line cross-sectional shape to concave, the invention addresses reliability issues that arise when scaling to finer pitches. This dimensional change in the vertical profile compensates for the reduced horizontal dimensions, allowing high-density integration while maintaining pattern formation reliability through improved stress and field distribution
3Length of moving object
If gate line width is reduced to achieve fine pitch, then device size decreases, but gate line reliability deteriorates
Solution Approach 1:
The invention compensates for the reduced gate line width by introducing a concave shape in the vertical dimension. This cross-sectional modification creates a more favorable stress and electrical field distribution pattern, allowing the gate line to maintain reliability even as its horizontal dimensions are reduced for finer pitch
Solution Approach 2:
The concave cross-sectional shape creates local variations in the gate line structure, with the central portion having a different profile than the lateral regions. This local quality change optimizes the electrical and mechanical properties specifically in the critical central region, maintaining reliability despite overall width reduction
Data Source
AI summary
In a semiconductor device including a gate line having a relatively narrow width and a relatively smaller pitch and a method of manufacturing the semiconductor device, the semiconductor device includes a substrate having a fin-type active region, a gate insulating layer that covers an upper surface and sides of the fin-type active region, and a gate line that extends and intersects the fin-type active region while covering the upper surface and the both sides of the fin-type active region, the gate line being on the gate insulating layer, wherein a central portion of an upper surface of the gate line in a cross-section perpendicular to an extending direction of the gate line has a concave shape.