Concave Inner Spacer Structure for Uniform GAA Nanosheet Isolation

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Solution Overview

Problem

In nanosheet GAA field effect transistor devices, non-uniformities in inner spacer thickness during the stacked nanosheet process flow can expose source/drain regions to etching gases and chemicals, degrading device performance due to variations in SiGe indentation and concave shapes at the interface between sacrificial nanosheet layers and gate sidewall spacers.

Innovation Solution

A semiconductor structure and method where the inner spacer is formed with a concave shape inverse to the typical concave shape observed in sacrificial nanosheet layers, featuring thicker portions at the interface between the inner spacer and gate sidewall spacer to provide uniform thickness and protect source/drain regions, achieved through partial recessing of sacrificial semiconductor layers, deposition of a sacrificial dielectric layer, and formation of sidewall spacers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional inner spacer formation is used in stacked nanosheet GAA process, then device density and performance are improved through wrap-around gate structures, but non-uniformities in inner spacer thickness expose source/drain regions to etching gases and chemicals, degrading device performance

Engineering Contradiction:
Improvedevice performanceVSAvoidinner spacer thickness uniformity
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies inversion by forming the inner spacer with a convex shape (opposite to the conventional concave shape) at the interface between the inner spacer and gate sidewall spacer. This convex configuration compensates for the concave indentation created by SiGe layer removal, ensuring uniform inner spacer thickness and preventing source/drain region exposure to etching gases and chemicals, thereby maintaining device performance and reliability

Inventive Principle:
Principle #13The other way round (Inversion)

Solution Approach 2:

The patent implements preliminary action by forming the convex inner spacer shape before the channel release etching process. This pre-formed convex structure acts as a protective barrier that prevents etching gases and chemicals from exposing the source/drain regions during subsequent processing steps, eliminating the need for additional protective measures and ensuring consistent device performance

Inventive Principle:
Principle #10Preliminary action

2Ease of manufacture

If SiGe indentation and concave shape formation are used to create inner spacer, then gate-all-around structure is achieved, but variations in SiGe indentation cause non-uniform inner spacer thickness that exposes source/drain regions

Engineering Contradiction:
Improvegate-all-around structure formationVSAvoidinner spacer thickness consistency
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent applies preliminary anti-action by intentionally forming a convex shape in the inner spacer that counteracts the concave indentation created by SiGe layer removal. This pre-compensating convex structure ensures that the final inner spacer maintains uniform thickness despite the underlying concave geometry, preventing source/drain region exposure and ensuring manufacturing precision while maintaining ease of gate-all-around structure formation

Inventive Principle:
Principle #9Preliminary anti-action

Data Source

PatentUS20240006496A1Semiconductor device with robust inner spacer
Publication Date: 2024.01.04 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US20240006496A1 patent drawing
  • US20240006496A1 patent drawing
  • US20240006496A1 patent drawing

AI summary

A semiconductor structure includes a plurality of semiconductor layers vertically stacked over a semiconductor substrate. Each of the plurality of semiconductor layers defining a channel region of the semiconductor structure. A source/drain region is located on opposite ends of the plurality of semiconductor layers while a metal gate stack surrounds each of the plurality of semiconductor layers. An inner spacer having a concave surface curving inward in a direction towards the source/drain region is located between each of the plurality of semiconductor layers for separating the metal gate stack from the source/drain region.