Concave Spacer for Semiconductor Interconnection Seam Prevention
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in forming reliable semiconductor device structures at increasingly smaller sizes, as the complexity of processing and manufacturing increases due to decreasing feature sizes, making it difficult to maintain geometric size reduction while preventing seam formation and ensuring structural reliability.
Innovation Solution
The use of a first spacer with a concave surface over the sidewall of the interconnection line, where the second angle between the spacer and the substrate is smaller than the angle between the interconnection line and the substrate, helps in reducing seam formation and improving structural reliability by being more tapered than the sidewall, thereby preventing seam formation and enhancing the geometric size reduction capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes are decreased to increase functional density, then productivity and cost efficiency are improved, but manufacturing complexity and difficulty increase
Solution Approach 1:
The spacer formation process is segmented into multiple etching stages (first spacer material layer etched to form first spacer, then second spacer material layer etched to form second spacer). This segmentation allows each etching process to be optimized independently, reducing the overall complexity of forming spacers at reduced feature sizes while maintaining high functional density.
Solution Approach 2:
The first spacer is formed in advance before the second spacer material layer is deposited. This preliminary action creates a foundation structure that guides subsequent processing steps, enabling precise control of the final spacer geometry even at reduced feature sizes, thereby managing manufacturing complexity while achieving high functional density.
2Productivity
If feature sizes are decreased to increase functional density, then productivity is improved, but manufacturing precision and reliability become more difficult to maintain
Solution Approach 1:
The spacer formation is divided into two separate etching operations with different spacer material layers. Each etching process can be independently optimized for precision, allowing the first spacer to be formed with specific geometric requirements and the second spacer to be formed with different precision requirements, thereby maintaining manufacturing precision even as feature sizes decrease.
Solution Approach 2:
Different spacer material layers are used at different locations and stages of the process. The first spacer material layer and second spacer material layer can have different properties optimized for their specific functions and locations, enabling precise control of local geometric features while maintaining overall manufacturing reliability at reduced feature sizes.
3Reliability
If spacers are formed with steeper angles to reduce seam formation, then structural reliability is improved, but geometric size reduction becomes more difficult
Solution Approach 1:
The spacer structure is segmented into two distinct spacers formed by separate etching processes. The first spacer can be formed with a first angle optimized for structural reliability and seam prevention, while the second spacer can be formed with a second angle optimized for geometric size reduction. This segmentation allows both conflicting requirements to be satisfied in different parts of the same structure.
Solution Approach 2:
The two spacers are formed with asymmetric angles relative to the substrate, where the first spacer has a different angle than the second spacer. This asymmetric design allows each spacer to be optimized for its specific function - one for structural reliability and seam prevention, and the other for enabling geometric size reduction, thereby resolving the contradiction between these two objectives.
Data Source
AI summary
Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a substrate having a first top surface, and an interconnection line over the first top surface of the substrate. The interconnection line has a sidewall. The semiconductor device structure also includes a first spacer over the sidewall of the interconnection line. The first spacer has a first concave surface which concaves towards the sidewall of the interconnection line. The semiconductor device structure further includes a dielectric layer covering the substrate, the interconnection line and the first spacer.