Concealing Logic Circuit for Optical Probing Attack Protection

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Solution Overview

Problem

Existing countermeasures against optical probing attacks are inefficient and do not adequately protect against the misuse of optical probing techniques for extracting sensitive information from integrated circuits.

Innovation Solution

The implementation of a concealing logic circuit that operates in the opposite mode of the target logic circuit, coupled with an evaluation circuit that generates complementary input signals, effectively camouflages the switching activity of the target logic circuit, making it difficult for adversaries to extract sensitive information through optical probing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of information

If optical probing techniques are used to extract sensitive information from integrated circuits, then information extraction capability is improved, but security against physical attacks deteriorates

Engineering Contradiction:
Improveinformation extraction capabilityVSAvoidsecurity against physical attacks
Core Design Contradiction:
Loss of informationVSReliability

Solution Approach 1:

The patent applies inversion by placing concealing logic circuits that operate in opposite mode to the target logic circuit. When the target circuit switches, the concealing circuit switches in the opposite direction, creating opposite optical signals that cancel each other out. This invert-based cancellation prevents optical probing attacks by making the optical signal appear constant regardless of target circuit state changes.

Inventive Principle:
Principle #13The other way round (Inversion)

Solution Approach 2:

The patent implements preliminary anti-action by pre-positioning concealing logic circuits near the target logic circuit before any attack occurs. These concealing circuits are designed to continuously generate counter-signals that oppose and neutralize the optical signals emitted by the target circuit, providing ongoing protection against optical probing attempts.

Inventive Principle:
Principle #9Preliminary anti-action

2Reliability

If conventional countermeasures such as protective shields or tamper-proof memories are implemented, then security protection is improved, but device complexity and manufacturing cost increase

Engineering Contradiction:
Improvesecurity protectionVSAvoiddevice complexity and manufacturing cost
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies universality by using standard logic circuit cells that serve dual purposes: the concealing logic circuits perform both their normal logical function and the security function of canceling optical signals. This eliminates the need for separate dedicated security components, reducing device complexity and manufacturing costs while maintaining security protection.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent implements self-service by having the concealing logic circuits automatically generate and apply their own counter-signals without external intervention. The circuits self-regulate to maintain optical signal cancellation, eliminating the need for additional control mechanisms or external monitoring systems.

Inventive Principle:
Principle #25Self-service

3Reliability

If concealing logic circuits are placed in close optical proximity to target logic circuits, then optical signal cancellation is improved, but area overhead increases

Engineering Contradiction:
Improveoptical signal cancellation effectivenessVSAvoidarea overhead
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent applies local quality by strategically positioning concealing logic circuits only in specific locations where optical signal cancellation is most effective—specifically in close optical proximity to the target logic circuits. This localized approach ensures optimal cancellation effectiveness while minimizing the total area overhead compared to uniform distribution.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent implements merging by integrating the concealing logic circuits into the same physical region as the target logic circuits, combining their functional spaces. This overlapping placement allows the concealing circuits to be in close optical proximity for effective cancellation while sharing the same area, thereby reducing overall area overhead.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach significantly increases the time and cost for an adversary to perform optical probing attacks, effectively protecting the target logic circuit against unauthorized access and information extraction.

Implementation Method 1

optical probing enables an adversary to steal the chip secretes... through physical attacks

Methodology Applied
Scientific EffectOptical probing:

Data Source

PatentUS12235959B1Apparatus for protecting against optical probing attacks
Publication Date: 2025.02.25 UNIV OF FLORIDA RESEARCH FOUNDATION INC
  • US12235959B1 patent drawing
  • US12235959B1 patent drawing
  • US12235959B1 patent drawing

AI summary

Methods and systems are directed to protect a target logic circuit against optical probing attacks and conceal a logic state in the target logic circuit. The method comprises designing a concealing logic circuit. The concealing logic circuit can be coupled to complement of input signals of the target logic circuit, inserted as neighbor logic circuit of the target logic circuit, and placed in close optical proximity to the target logic circuit. The concealing logic circuit can operate in the opposite operation mode or logic state of the target logic circuit in response to the complement of the input signals to the target logic circuit. The method can further comprise designing an evaluation circuit that generates the complement of the input signals and minimizes a path delay between the target logic circuit input and the concealing logic circuit input.