Concentric Vertical Capacitor Structure for Dense 3D NAND
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Solution Overview
Problem
Current capacitor structures in 3D-NAND technology face challenges in achieving high capacitance density while maintaining a small footprint, as they require additional chip area and are prone to time-dependent dielectric breakdown, which is exacerbated by the increasing number of metal lines and shrinking chip space.
Innovation Solution
A novel vertical-type capacitor structure is introduced, where concentrically arranged conductive plates extend from the top to the bottom surface of the substrate, surrounded by an insulating structure, allowing for high capacitance density without occupying excessive space and preventing electrical interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If additional plates are introduced to achieve high capacitance density, then capacitance density is improved, but chip area increases
Solution Approach 1:
The patent transitions from planar capacitor structures to vertical three-dimensional structures. The capacitor plates are arranged vertically with one plate extending from the first main surface to the second main surface of the substrate, and another plate extending from the second main surface through the substrate to the first main surface, utilizing the vertical dimension to achieve high capacitance density without increasing chip area.
Solution Approach 2:
The patent implements a nested configuration where capacitor plates are concentrically arranged around a central axis. The first plate and second plate are positioned concentrically with respect to each other, creating a nested structure that maximizes capacitance within a compact footprint by utilizing radial space around a central void or core structure.
2Quantity of substance
If capacitor area is increased to meet circuit requirements, then capacitance is improved, but time-dependent dielectric breakdown failure rate increases
Solution Approach 1:
By transitioning to vertical capacitor structures that extend through the substrate thickness, the patent achieves the required capacitance values without increasing the planar area of the capacitor. This dimensional transition reduces the stressed dielectric volume and minimizes the probability of dielectric breakdown while maintaining or enhancing capacitance.
Solution Approach 2:
The patent changes the geometric parameters of the capacitor structure from planar to vertical, and from parallel plates to concentric cylindrical plates. This parameter change allows achieving higher capacitance density in a smaller volume, thereby reducing the overall dielectric stress and improving reliability by lowering the time-dependent dielectric breakdown failure rate.
3Area of stationary object
If chip area is reduced for scaling, then device density is improved, but space for additional components is reduced
Solution Approach 1:
The patent utilizes the vertical dimension by forming capacitor plates that extend through the substrate thickness and arranging them concentrically. This three-dimensional configuration achieves high capacitance density without consuming additional planar chip area, thereby preserving space for other electronic components while meeting scaling requirements.
Data Source
Figure 1A~1B
Figure 2A~2B
Figure 3A~3B
AI summary
A capacitor is provided. The capacitor includes a substrate that has opposing first and second main surfaces. The capacitor also includes at least two conductive plates that are formed in the substrate and extend from the first main surface to the second main surface of the substrate. The capacitor further includes at least one insulating structure that is formed between two adjacent conductive plates of the at least two conductive plates and extends from the first main surface to the second main surface.