Concentric Stacked Via Structure for Integrated Circuit Signal Routing
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Solution Overview
Problem
Modern very large scale integrated (VLSI) circuits face challenges in efficiently connecting multiple processor cores, caches, and interface units due to complex wiring systems, where existing via structures often require bends and directional changes to avoid other wires and vias, leading to increased resistance and capacitance in long-distance signal paths.
Innovation Solution
A concentric arrangement of stacked vias is implemented, where each via extends vertically from its respective metal layer to the silicon layer without bends, with those on higher metal layers closer to the center and those on lower layers closer to the perimeter, allowing long-distance signal lines to be straight and minimizing resistance and capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional via structures are used to connect signal lines on multiple metal layers to the silicon layer, then connections can be established, but the signal paths require bends and directional changes to avoid other wires and vias, increasing resistance and capacitance
Solution Approach 1:
The via connection structure is segmented into multiple via types (first type vias for outer metal layers, second type vias for inner metal layers) with different positioning strategies. Outer layer vias are positioned closer to the center of the via structure, while inner layer vias are positioned closer to the perimeter, allowing each via to have an optimized straight path to its respective metal layer without interference from other connections.
Solution Approach 2:
The patent utilizes the vertical dimension (z-axis) by stacking multiple metal layers above the silicon layer, with each layer positioned at a different height. This vertical stacking allows signal lines on different layers to be connected to the same via structure through straight vertical paths, eliminating the need for horizontal bends and directional changes that would increase resistance and capacitance.
2Adaptability or versatility
If signal lines traverse multiple metal layers to connect various agents, then complex wiring requirements are met, but the signal paths become longer with more bends, increasing resistance and capacitance
Solution Approach 1:
Multiple via structures are nested within a shared predefined area on the silicon layer. Each via structure contains multiple vias at different metal layers that all connect to the same underlying circuitry through straight vertical paths. This nesting allows complex multi-layer wiring to be achieved while maintaining straight signal paths, as each via is positioned to connect directly to its metal layer without bends.
3Area of stationary object
If vias are positioned to accommodate all metal layer connections in a compact area, then area efficiency is improved, but via placement becomes more constrained requiring non-straight paths
Solution Approach 1:
Different regions within the via structure are assigned different via types based on their vertical position. The center region accommodates first type vias for outer metal layers, while the perimeter region accommodates second type vias for inner metal layers. This local differentiation allows each via to be positioned optimally for its specific metal layer connection, maintaining straight paths while packing multiple connections into a compact area.
Data Source
AI summary
An integrated circuit (IC) having a concentric arrangement of stacked vias is disclosed. The IC includes first and second pluralities of signal lines on first and second metal layers, respectively. The second metal layer is arranged between the first metal layer and a silicon layer. The IC also includes a via structure implemented in a predefined area, and connects each of the first and second pluralities of signal lines to circuitry in the silicon layer through respective first and second pluralities of vias. Each via of the first and second pluralities has a center point that extends along a vertical axis from its respective metal layer to the silicon layer. Centers of each of the second plurality of vias are closer to a perimeter of the predefined area than respective centers of any of the first plurality of vias.