Concentric TFT Electrode Layout to Suppress the Hump Effect
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Solution Overview
Problem
Current thin film transistors in display devices face reliability issues due to the 'hump effect' caused by uneven gate insulating layer thickness, leading to shifted threshold voltage and reduced durability when driving light-emitting units, which requires a solution to enhance current handling and transistor reliability.
Innovation Solution
The implementation of a display device with multiple thin film transistors connected in parallel, where the gate and source/drain layers are disposed in a concentric manner to ensure uniform channel and gate layer thickness, reducing the sloped profile of edge regions and minimizing electron or hole trapping, thereby increasing the durability and reliability of the transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single transistor is used to drive a light-emitting unit, then the device structure is simple, but the transistor suffers excessive current which shortens lifespan and decreases reliability
Solution Approach 1:
The patent divides a single transistor into multiple transistors (first transistor and second transistor) connected in parallel. Each transistor handles a portion of the total current, reducing the current burden on individual devices and improving reliability while maintaining the driving capability for the light-emitting unit.
2Ease of manufacture
If conventional transistor structure with sloped edge regions is used, then manufacturing is easier, but the gate insulating layer has uneven thickness causing hump effect and threshold voltage shift
Solution Approach 1:
The patent introduces curved portions at the edges of the gate electrode and source/drain electrodes, replacing the conventional sharp angular edges. This curvature design ensures that the gate insulating layer maintains uniform thickness across the entire gate region, including edge areas, thereby preventing the hump effect and threshold voltage shift while remaining compatible with standard manufacturing processes.
3Reliability
If multiple transistors are integrated to provide large current, then transistor durability increases, but device complexity increases
Solution Approach 1:
The patent merges multiple transistors into a single integrated structure where the first and second transistors share common components (gate insulating layer, channel layer, and electrode connections). This integration achieves the current-sharing benefit of multiple transistors while minimizing the increase in device complexity through shared structural elements.
Solution Approach 2:
The patent employs a nested configuration where the gate electrode of one transistor is positioned within or adjacent to the structure of another transistor, and source/drain regions are arranged in an interleaved manner. This nesting approach maximizes space utilization and reduces the overall footprint of the multi-transistor structure, thereby limiting the increase in device complexity.
Data Source
AI summary
An electronic device is provided. The electronic device includes a substrate, a material layer, a first metal layer, and a second metal layer. The material layer is disposed on the substrate, wherein a material of the material layer includes polysilicon, amorphous silicon, or indium gallium zinc oxide. The first metal layer is disposed on the material layer, wherein a first edge of the first metal layer includes a first curved portion. The second metal layer is disposed on the material layer, wherein a second edge of the second metal layer includes a second curved portion, and the second edge surrounds the first edge.