Concise Cache Coherence Directory for Multi-Compute-Engine Systems
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Solution Overview
Problem
Directory-based cache coherence protocols in multi-compute-engine systems face scalability issues due to increasing storage overhead, latency, and power consumption as the number of processors grows, making them impractical for systems with a high number of cores.
Innovation Solution
Implementing a concise cache coherence directory (CDir) that reduces storage size by aggregating common sharing patterns and using a two-fold approach to minimize sharing vectors and directory entries, allowing for efficient cache coherence maintenance with reduced latency and storage overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If directory-based cache coherence protocols are used in multi-compute-engine systems, then cache coherence can be maintained, but storage overhead increases linearly with the number of processors
Solution Approach 1:
The patent merges multiple cache line tracking entries into a single shared entry when multiple cache lines are accessed by the same set of processors in the same temporal pattern. This consolidation reduces the number of directory entries from O(N*M) to O(N), where N is the number of processors and M is the number of cache lines, thereby reducing storage overhead while maintaining cache coherence tracking capability.
Solution Approach 2:
The patent creates a universal shared directory entry that can track multiple cache lines simultaneously. This multi-functional entry serves the purpose of monitoring coherence for multiple cache lines that share the same access pattern, replacing what would traditionally require multiple separate entries, thus reducing overall storage requirements.
2Reliability
If directory-based cache coherence protocols are used, then cache coherence is maintained, but latency increases with the number of processors
Solution Approach 1:
By merging tracking of multiple cache lines into a single shared entry, the patent reduces the number of directory lookups required during coherence operations. When cache lines share the same access pattern, a single shared entry can service coherence requests for all of them, thereby reducing latency proportional to the number of merged entries.
3Reliability
If directory-based cache coherence protocols are used, then cache coherence is maintained, but power consumption increases with the number of processors
Solution Approach 1:
The patent reduces power consumption by merging directory entries, which directly reduces the number of active memory locations that need to be monitored and updated. Fewer directory entries mean fewer memory accesses, less signal switching, and lower dynamic power consumption in the directory structure, while still maintaining full cache coherence functionality.
4Reliability
If traditional cache coherence directories are used, then all cache lines can be tracked, but device complexity increases with the number of processors
Solution Approach 1:
The patent simplifies the directory structure by merging multiple cache line tracking functions into shared entries. This consolidation reduces the total number of directory structures needed, simplifies the indexing mechanism, and reduces the complexity of coherence protocol implementation, while maintaining the ability to track all cache lines through the shared entries.
Data Source
AI summary
Methods and systems for providing cache coherence in multi-compute-engine systems are described herein. In on example, concise cache coherency directory (CDir) for providing cache coherence in the multi-compute-engine systems is described. The CDir comprises a common pattern aggregated entry for one or more cache lines from amongst a plurality of cache lines of a shared memory. The one or more cache lines that correspond to the common pattern aggregated entry are associated with a common sharing pattern from amongst a predetermined number of sharing patterns that repeat most frequently in the region.