Concise Data for Formal Verification Checker Completeness
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing electronic design automation (EDA) tools face challenges in providing concise data for analyzing checker completeness during formal verification of digital circuit designs, leading to inefficiencies in determining necessary manual actions to achieve full coverage, as current coverage metrics can overestimate the sufficiency of property sets and are difficult for human users to interpret.
Innovation Solution
The method involves collecting checker start-point signals and traversing netlists to identify structural and functional COI signals, determining interest signals, and ranking them by probable impact on reducing coverage holes, with a graphical user interface providing concise data for users to focus on key signals for additional checkers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional coverage metrics are used to assess checker completeness, then verification coverage can be measured, but the metrics can overestimate coverage and are difficult for human users to interpret
Solution Approach 1:
The patent extracts only the essential uncovered signals from the complete verification coverage data, presenting a condensed list of critical signals that need additional checkers. This extraction approach removes unnecessary complexity from traditional coverage metrics while maintaining measurement accuracy, making it easier for users to identify what needs verification without being overwhelmed by comprehensive but hard-to-interpret coverage data.
2Reliability
If comprehensive coverage analysis is performed to ensure full verification coverage, then checker completeness can be assessed, but manual effort and time to achieve full coverage increase
Solution Approach 1:
The system automatically performs comprehensive coverage analysis and generates prioritized lists of uncovered signals without requiring manual intervention. The tool self-services by identifying, analyzing, and presenting the critical verification gaps, allowing verification engineers to achieve full coverage more efficiently by focusing on the automatically identified high-priority signals rather than performing manual coverage analysis.
Solution Approach 2:
The patent implements a feedback mechanism that continuously monitors verification coverage and provides actionable insights about uncovered signals. By analyzing the results of formal verification and automatically identifying gaps in coverage, the system provides feedback that guides verification engineers on what additional checkers to write, reducing the time and effort needed to achieve complete coverage while maintaining high reliability.
3Measurement precision
If detailed analysis of all signals is performed to identify coverage gaps, then complete checker completeness can be determined, but device complexity and computational resources increase
Solution Approach 1:
The patent extracts and focuses only on the most critical uncovered signals that have the greatest impact on verification completeness. Rather than analyzing all signals in detail, the system identifies and presents a prioritized subset of signals that require additional checkers, reducing computational complexity while maintaining precise measurement of checker completeness through targeted analysis of high-impact signals.
Data Source
AI summary
Methods and systems for providing concise data for analyzing checker completeness, in the context of formal verification analysis of circuit designs. The methods and systems concisely report information useful to a human user (e.g., circuit designer or verification engineer) for efficiently determining what manual action should be taken next to resolve holes in verification coverage. The reported information can include lists of signals on which checkers can be written, which lists can be ranked, can be limited to a subset of interest signals, and can include corresponding cover items for each reported interest signal. The present systems and methods thereby improve on reporting provided to the user, permitting the user to more quickly advance a formal verification process toward full coverage of the relevant portions of a circuit design.