Concurrency Manager for Automated Parallel Execution
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Solution Overview
Problem
Programmers with a deep understanding of optimization and simulation problems often struggle to effectively utilize concurrency in processing systems due to the complexity of writing application code that leverages multiple processor cores and resources, leading to underutilization of available concurrency capabilities.
Innovation Solution
An apparatus and method that simplifies the execution of concurrent and repetitive operations by identifying an instruction block and a trigger instruction within application code, allowing multiple instances to be executed independently across processor cores without requiring explicit threading logic, and reorganizing data structures to optimize resource allocation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If programmers write application code to utilize concurrency with multiple processor cores, then processing efficiency and resource utilization are improved, but code complexity and difficulty of implementation increase
Solution Approach 1:
The patent introduces a concurrency manager as an intermediary component that handles thread creation, scheduling, and coordination. This mediator abstracts the complexity of concurrent programming from the application code, allowing developers to write simpler sequential-like code while the manager handles the intricate concurrency management underneath, thus resolving the contradiction between achieving high processing efficiency and maintaining code simplicity
Solution Approach 2:
The system employs self-service mechanisms where the concurrency manager automatically manages thread lifecycle, resource allocation, and synchronization without requiring explicit instructions from the application code. The trigger instruction mechanism allows the system to autonomously identify and execute concurrent operations, eliminating the need for programmers to manually configure complex threading logic while still achieving optimized processing efficiency
2Quantity of substance
If explicit threading logic is used to execute multiple instances of code concurrently, then resource utilization is improved, but syntax complexity and programming burden increase
Solution Approach 1:
The patent extracts the threading and concurrency management logic from the application code into a separate, dedicated concurrency manager. The application code only contains the trigger instruction and simple task definition, while all the complex threading infrastructure, scheduling algorithms, and resource management are extracted and handled by the manager, thus reducing programming burden while maintaining high resource utilization
Solution Approach 2:
The trigger instruction mechanism serves multiple functions: it marks the beginning of a concurrent task block, provides metadata about the task, and triggers the concurrency manager to create appropriate thread instances. This multi-functional approach eliminates the need for separate syntax elements for task definition and concurrency activation, simplifying the programming interface while enabling efficient resource utilization across multiple cores
Data Source
AI summary
A processor core receives a request to execute application code including a trigger instruction and an instruction block that reads a row of data values from a data structure and outputs a data value from a function using the row as input. The data structure is divided into multiple portions and the trigger instruction indicates that multiple instances of the instruction block are to be executed concurrently. In response to the request and to identification of the instruction block and trigger instruction, the processor core generates multiple instances of a support block that causes independent repetitive execution of each instance of the instruction block until all rows of the corresponding portion of the data structure are used as input. The processor core assigns instances of the instruction and support blocks to multiple processor cores, and provides each instance of the instruction block with the corresponding portion of the data structure.