Concurrent Actor Language Circuit Translation

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Solution Overview

Problem

Current EDA systems cannot efficiently map sequential programs into concurrent circuit implementations, as sequential programming languages obscure concurrency and assume all data resides in one globally accessible memory, making them unsuitable for concurrent circuit designs.

Innovation Solution

A method and apparatus that specify a program using a concurrent programming language with constructs defining processes and communication channels, transforming the representation into a hardware description language (HDL) to implement efficient concurrent circuit designs by generating a hierarchy of HDL constructs that represent processes and channels in hardware.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If sequential programming languages are used to specify circuit designs, then the programming is simpler and more familiar to developers, but the concurrency available in the algorithm is obscured and the specification is not suited for concurrent circuit implementations

Engineering Contradiction:
Improveease of programmingVSAvoidconcurrency implementation efficiency
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The patent introduces an intermediate concurrent programming language (such as CAL - Concurrent Actor Language) that serves as a mediator between sequential programming and hardware description languages. This intermediate language explicitly models concurrency through actor processes and communication channels, allowing the concurrency structure to be preserved and efficiently mapped to hardware while maintaining programming simplicity through high-level abstractions.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Device complexity

If sequential programming languages assume all data resides in one globally accessible memory, then the memory model is simpler, but this assumption is not suited for concurrent circuit implementations which require distributed memory structures

Engineering Contradiction:
Improvememory model complexityVSAvoidconcurrent circuit implementation suitability
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent segments the globally accessible memory model into distributed memory structures associated with individual actor processes. Each actor has its own local memory space, and communication between actors occurs through explicit message passing over communication channels. This segmentation enables efficient mapping to distributed hardware memory structures while maintaining a simplified programming model through the actor abstraction.

Inventive Principle:
Principle #1Segmentation

3Ease of manufacture

If EDA systems use traditional translation methods from sequential code to hardware, then the translation process is straightforward, but the resulting circuit implementation is not efficient for concurrent operations

Engineering Contradiction:
Improvetranslation process simplicityVSAvoidcircuit implementation efficiency
Core Design Contradiction:
Ease of manufactureVSProductivity

Solution Approach 1:

The patent performs preliminary transformation of the sequential program into a concurrent actor model representation before generating the final hardware description language code. This preliminary action explicitly identifies and models the concurrent structure, communication patterns, and data flow of the algorithm, enabling the subsequent hardware generation to produce efficient concurrent circuit implementations rather than forcing a sequential structure onto parallel hardware.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS7496869B1Method and apparatus for implementing a program language description of a circuit design for an integrated circuit
Publication Date: 2009.02.24 XILINX INC
  • US7496869B1 patent drawing
  • US7496869B1 patent drawing
  • US7496869B1 patent drawing

AI summary

Method and apparatus for implementing a program language description of a circuit design for an integrated circuit is described. In one example, a program is specified using a concurrent programming language. The program includes programming constructs that define a plurality of processes and a plurality of communication channels. A hierarchy of elements that classify the programming constructs of the program are generated to produce a transformed representation. A hardware description language (HDL) representation of the circuit design is generated from the transformed representation by translating the hierarchy of elements to a hierarchy of HDL constructs that implements the plurality of processes and the plurality of communication channels in hardware.