Concurrent Address Translation Lookups for Emulator Performance
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Solution Overview
Problem
Emulators face performance issues due to slower address translation data lookups, particularly when simulating device operations without the actual device, as existing methods do not efficiently utilize concurrent processing to optimize address translation.
Innovation Solution
Concurrently performing address translation data lookups on multiple threads, where one thread performs a translation lookaside buffer lookup while another thread speculatively performs a page table entry lookup, using spinloops for synchronization and data sharing between threads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If sequential address translation lookups are performed in an emulator, then address translation accuracy is maintained, but emulation speed deteriorates
Solution Approach 1:
The patent initiates a speculative page table entry lookup in advance on a second thread before the translation lookaside buffer lookup completes on the first thread. This preliminary action allows the system to prepare address translation data ahead of time, reducing the overall lookup time while maintaining accuracy through validation against the TLB result.
Solution Approach 2:
The patent implements concurrent lookups on multiple threads that can proceed simultaneously rather than sequentially. The first thread performs TLB lookup while the second thread performs speculative PTE lookup, ensuring that useful computational action continues on both threads without idle waiting time, thereby improving emulation speed while preserving translation accuracy through result validation.
2Loss of time
If concurrent lookups are performed on multiple threads, then address translation time is reduced, but system complexity increases
Solution Approach 1:
The patent uses a validation mechanism as an intermediary that coordinates the results from multiple concurrent lookups. The speculative PTE lookup result is validated against the TLB lookup result to ensure correctness, providing a simple mediation approach that manages thread coordination without requiring complex synchronization protocols.
Solution Approach 2:
The patent creates a copy of the address translation lookup operation by executing identical lookup logic on two different threads with different data sources (TLB and page table). This copying approach simplifies thread coordination because both threads perform the same validated operation independently, requiring only result comparison rather than complex inter-thread communication.
3Speed
If speculative lookups are performed, then lookup speed is improved, but reliability of address translation may deteriorate
Solution Approach 1:
The patent implements a feedback mechanism where the result of the speculative PTE lookup is validated against the TLB lookup result. If the speculative result matches the TLB result, the lookup succeeds; if not, the speculative lookup is discarded and the TLB result is used. This feedback loop ensures that speculative execution improves speed without compromising the reliability of the final address translation.
Solution Approach 2:
The speculative PTE lookup serves as a preliminary action that prepares potential address translation results in advance. However, this preliminary result is not committed until validated against the definitive TLB lookup, ensuring that while speed is improved through early preparation, reliability is maintained through subsequent validation.
Data Source
AI summary
Various technologies and techniques are disclosed for concurrently performing address translation data lookups for use by an emulator. On a first thread, a first lookup is performed for address translation data for use by an emulator. On a second thread, a second lookup for the address translation data is concurrently and speculatively performed. The address translation data from a successful lookup from either the first lookup or the second lookup is used to map a simulated physical address to a virtual address of the emulator. For example, the first thread can perform a translation lookaside buffer lookup while the second thread concurrently and speculatively performs a page table entry lookup for the address translation data.