Concurrent Address Translation for Disaggregated Memory Sharing

Solution Overview

Problem

Existing disaggregated memory environments lack efficient memory resource utilization and optimization, particularly when host memory resources are added, leading to minimal performance improvements and inefficient memory access.

Innovation Solution

Implementing concurrent address translation schemes using a virtual address manager to assign either local or shared virtual addresses based on application needs, enabling a uniform global address translation scheme that optimizes memory resource allocation and access.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If host memory resources are added to disaggregated memory environments, then memory capacity increases, but memory resource utilization efficiency deteriorates

Engineering Contradiction:

Improvememory capacityVSAvoidmemory resource utilization efficiency

Core Design Contradiction:

Quantity of substanceVSProductivity

Solution Approach 1:

The patent segments memory resources into local memory (coupled to specific hosts) and shared memory (accessible by multiple hosts), with separate address translation mechanisms for each. The address translation component determines whether to use local or shared address translation based on the memory access request, enabling efficient utilization of both memory types without resource conflicts.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic address translation that adapts to different memory access patterns. The address translation component dynamically selects between local and shared address translation schemes based on real-time memory access requests, allowing the system to optimize performance for both capacity-intensive and speed-intensive workloads.

Inventive Principle:

Principle #15Dynamics

2Device complexity

If conventional address translation is used in disaggregated memory, then implementation is simple, but memory access efficiency deteriorates

Engineering Contradiction:

Improveaddress translation implementationVSAvoidmemory access efficiency

Core Design Contradiction:

Device complexityVSProductivity

Solution Approach 1:

The patent implements dynamic address translation that adapts to different memory access patterns. The address translation component dynamically selects between local and shared address translation schemes based on real-time memory access requests, allowing the system to optimize performance for both capacity-intensive and speed-intensive workloads.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The address translation component acts as an intermediary between memory controllers and memory devices, intelligently determining whether to translate addresses using local or shared schemes. This intermediary layer enables efficient memory access without requiring complex changes to existing memory controllers or applications.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Speed

If local address translation is used for all memory accesses, then memory access speed is maintained, but memory resource sharing capability deteriorates

Engineering Contradiction:

Improvememory access speedVSAvoidmemory resource sharing capability

Core Design Contradiction:

SpeedVSAdaptability or versatility

Solution Approach 1:

The patent segments memory resources into local memory (coupled to specific hosts) and shared memory (accessible by multiple hosts), with separate address translation mechanisms for each. The address translation component determines whether to use local or shared address translation based on the memory access request, enabling efficient utilization of both memory types without resource conflicts.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The address translation component provides universal address translation capability that handles both local and shared memory access scenarios. It can translate addresses for local memory to maintain high speed access, and simultaneously translate addresses for shared memory to enable resource sharing across multiple hosts, making the system adaptable to different workload requirements.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250315376A1Concurrent address translation schemes for memory sub-systems in a disaggregated memory environment

Publication Date: 2025.10.09 MICRON TECHNOLOGY INC

AI summary

A processing device in a system receives a first request for a first set of memory addresses. The processing device determines, based on the first request, whether to assign a first set of physical addresses of a portion of physical addresses of a memory device as the first set of memory addresses. Responsive to determining not to assign the first set of physical addresses, the processing device requests a first set of virtual addresses of a plurality of contiguous virtual addresses. A first portion of virtual addresses of the plurality of contiguous virtual addresses contiguously maps to a second portion of physical addresses of the memory device. The processing device stores data to a second set of physical addresses contiguously mapped to the first set of virtual addresses.