Concurrent Branch Address Prediction and Register Update
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Solution Overview
Problem
In computing environments, the expensive process of loading branch addresses into special purpose registers for register-indirect branching leads to performance limitations due to the need to store values in additional registers, causing stalls during branch prediction before the values are loaded.
Innovation Solution
A method is implemented to predict the branch address and store it in a selected location concurrently with processing, allowing speculative execution using the predicted value, which is also stored in an affiliated register for further processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the branch address is loaded into a special purpose register via a general purpose register, then the register-indirect branch can be executed, but the called subroutine stalls due to data access before the value is loaded
Solution Approach 1:
The patent predicts the branch address value before the actual branch instruction executes. The predicted value is pre-loaded into the special purpose register (CTR) and affiliated register (R12) concurrently with processing the branch instruction, eliminating the need to wait for the sequential load operation to complete.
Solution Approach 2:
The patent creates a copy of the predicted branch address value and stores it in both the special purpose register (CTR) and the affiliated general purpose register (R12). This copying approach allows the called subroutine to immediately access the value without stalling, while maintaining the required ABI interface.
2Adaptability or versatility
If the branch address is stored in an additional register (R12) for ABI compliance, then the called function can use it as a base register, but the process becomes expensive and slow
Solution Approach 1:
The patent pre-loads the predicted branch address into both the special purpose register (CTR) and the affiliated general purpose register (R12) concurrently with branch instruction processing. This preliminary action eliminates the sequential load-store operations that cause time loss while maintaining ABI compatibility.
Solution Approach 2:
The patent combines the branch target address calculation with the register update operations. The same predicted value is simultaneously written to both CTR and R12 in a single concurrent operation, eliminating separate load and store instructions that would otherwise be required for ABI compliance.
3Productivity
If branch prediction is made before R12 value is loaded, then speculative processing can proceed, but the called subroutine stalls responsive to data access
Solution Approach 1:
The patent copies the predicted branch address value to both the special purpose register (CTR) and the affiliated general purpose register (R12). This ensures that when speculative processing needs to access R12, the value is already available, preventing stalls while maintaining prediction accuracy.
Data Source
AI summary
A value to be used in register-indirect branching is predicted and concurrently stored in a selected location accessible to one or more instructions. The value may be a target address used by an indirect branch and the selected location may be a hardware register, providing concurrent prediction of branch addresses and the update of register contents.