Concurrent Buffering and Layer Assignment in IC Layout
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Solution Overview
Problem
As integrated circuit design scales down, the increased resistivity of finer metal layer widths and longer interconnect delays require more buffers, leading to inefficient use of active silicon and routing area, making it challenging to meet electrical and timing constraints effectively.
Innovation Solution
The method involves inserting buffers and sizing metal interconnects for each net to meet timing skew constraints, promoting long nets to higher layers if necessary, and systematically demoting non-critical nets to minimize high-layer resource usage, while ensuring optimal timing and efficient resource utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If more buffers are inserted to reduce interconnect delay, then timing constraints are met, but active silicon and routing area increase
Solution Approach 1:
The patent transitions from a two-dimensional routing plane to a three-dimensional solution by utilizing multiple metal layers. Instead of adding more buffers in the same plane, the invention routes signals through different vertical layers (e.g., moving from metal layer 1 to metal layer 2), thereby reducing interconnect delay without increasing buffer count or routing area in any single layer.
Solution Approach 2:
The invention changes the routing parameters by selecting different metal layers based on net criticality and timing requirements. Non-critical nets are assigned to lower layers while critical nets use higher layers with better timing characteristics. This parameter-based assignment optimizes the balance between timing performance and resource utilization without requiring additional buffers.
2Reliability
If buffer insertion is increased to meet interconnect timing requirements, then timing performance improves, but device complexity increases
Solution Approach 1:
The patent resolves timing issues by exploiting the vertical dimension through multiple metal layers rather than increasing buffer insertion. By routing critical signals through higher metal layers that offer lower resistance and better timing characteristics, the invention achieves timing requirements with minimal buffer insertion, thereby reducing device complexity.
Solution Approach 2:
The invention dynamically changes routing parameters by selecting appropriate metal layers based on net criticality analysis. Critical nets are assigned to layers with superior timing characteristics, while non-critical nets use standard layers. This selective parameter assignment meets timing requirements without uniformly increasing buffer insertion across all nets.
3Quantity of substance
If metal layer width is reduced for scaling, then circuit density increases, but resistivity increases and interconnect delays worsen
Solution Approach 1:
The patent compensates for increased resistivity in scaled-down metal layers by utilizing vertical routing across multiple layers. Critical interconnects are routed through higher metal layers that maintain better electrical characteristics even as technology scales. This multi-layer approach mitigates the harmful effects of reduced metal width without sacrificing circuit density.
Solution Approach 2:
The invention changes the effective resistivity parameter by selecting metal layers with different electrical characteristics. As technology scales and lower layers experience higher resistivity, the system dynamically assigns critical nets to higher layers that offer lower resistance paths, thereby compensating for the inherent resistivity increase due to scaling while maintaining high circuit density.
Data Source
AI summary
A method and system for concurrent buffering and layer assignment in integrated current layout. Buffers are inserted and metal interconnects or “wires” are sized for every net, which consists of one driver and one or more receivers, such that timing skew constraints can be met. Long nets are promoted to a higher level if the slew violation can be fixed only by a promotion of the net or if the “slack” gain available by this promotion is equal to or greater than a predesignated layer of promotion threshold. In response to determining these layer assignments, the method and system then systematically demotes nets that are not critical and which do not impact the circuit and electrical constraints in order to minimize the use of high layer wire resources.