Concurrent Shared Cache Line Updates via FNC Instructions
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Solution Overview
Problem
In multi-processor computing environments, the frequent updating of shared data fields leads to performance degradation due to the overhead of compare and swap operations, which block other processors and cause cache coherence issues, making it impractical for frequent updates to counters or shared-modifiable structures.
Innovation Solution
The introduction of a Fetch due to Non-Coherent Store (FNC) instruction allows multiple processors to concurrently update a shared cache line without exclusive ownership, using a shared-modifiable cache directory state, enabling non-blocking atomic operations and reducing serialization overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If compare and swap instructions are used to update shared data fields, then data integrity is maintained, but processing speed deteriorates due to blocking other processors and causing cache coherence issues
Solution Approach 1:
The patent segments the cache line into multiple fields that can be independently updated by different processors. Each field has its own update counter, allowing concurrent updates to different fields within the same cache line without requiring global serialization, thus maintaining data integrity while improving processing speed
Solution Approach 2:
The patent introduces an intermediary mechanism (update counters and field-level tracking) that mediates between multiple processors attempting to update shared data. This intermediary tracks which fields are being updated by which processors, enabling coordinated concurrent updates without blocking, thereby maintaining reliability while enhancing productivity
2Productivity
If unique individual processor related fields are updated to minimize overhead, then processing speed improves, but system complexity increases
Solution Approach 1:
The patent merges the benefits of unique field updates with shared cache line updates by allowing multiple processors to update different fields within the same cache line concurrently. This combines the speed advantage of unique updates with the efficiency of shared cache utilization, improving processing speed without proportionally increasing system complexity
3Loss of information
If frequent updates are performed on shared cache lines, then data currency is improved, but performance deteriorates due to serialization overhead and cross-invalidate operations
Solution Approach 1:
The patent introduces dynamic field-level tracking where update counters and field ownership are dynamically adjusted based on which processors are updating which fields. This dynamic approach allows the system to adapt to varying update patterns, enabling frequent updates to different fields without requiring global serialization, thus maintaining data currency while preserving performance
Data Source
AI summary
A shared cache line is concurrently modified by multiple processors of a computing environment. The concurrent modification is performed based, at least, on receiving one or more architected instructions (Fetch due to Non-Coherent Store instructions) that permit multiple processors to concurrently update the shared cache line absent obtaining a lock or having exclusive ownership of the data.