Concurrent Circuit Design Initialization via Parent-Child Placer Updates
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Solution Overview
Problem
In circuit design flows, delays occur due to child placer processes waiting for the parent placer process to complete initialization and floorplanning, as they rely on data generated by the parent process for detailed placement.
Innovation Solution
The parent process generates an initial intermediate representation of the circuit design and provides incremental updates, allowing child processes to start concurrently and apply these updates in parallel, reducing the time required for initialization and floorplanning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the parent placer process completes initialization and floorplanning before child placer processes begin, then the child processes can receive complete design data, but the child processes experience significant waiting delays
Solution Approach 1:
The parent placer process performs preliminary initialization and floorplanning actions, generating design data that is made available to child processes before the parent completes all processing. This allows child processes to begin loading and processing data in advance, reducing waiting delays while ensuring data completeness through incremental updates.
Solution Approach 2:
The system maintains continuous useful action by enabling child placer processes to continuously load and process design data as it becomes available from the parent process, rather than idle-waiting. The incremental update mechanism ensures that child processes can continuously work with the most current data without interruption.
2Stability of the object's composition
If child placer processes wait for complete initialization data from the parent process, then data consistency is maintained, but the overall placement time increases significantly
Solution Approach 1:
The parent process performs preliminary initialization to create a baseline design data structure that child processes can immediately begin using. This preliminary action establishes data consistency from the start while allowing children to proceed without waiting for complete initialization, thereby improving placement speed without sacrificing stability.
Solution Approach 2:
The incremental update mechanism implements feedback by continuously notifying child processes when new design data becomes available from the parent process. This feedback loop allows child processes to maintain data consistency by periodically syncing with the parent while continuously processing, thus improving productivity without compromising data stability.
3Measurement precision
If the parent process generates all initialization data before starting child processes, then data accuracy is ensured, but the total processing time increases due to sequential execution
Solution Approach 1:
The parent process performs preliminary initialization to generate the foundational design data structure before child processes begin. This preliminary action ensures data accuracy is established from the outset while allowing child processes to concurrently process this initial data, thereby reducing total processing duration without sacrificing measurement precision.
Solution Approach 2:
The system maintains continuous useful action by enabling child processes to continuously process design data as it becomes available through incremental updates from the parent process. This continuous processing eliminates idle waiting time while the parent process continues generating accurate design data, thus reducing processing duration while maintaining data accuracy.
Data Source
AI summary
Disclosed approaches for processing a circuit design include providing access to checkpoint data of a design checkpoint of a circuit design and starting child processes by a parent process. An initial intermediate representation is generated by the parent process, and concurrent with the generating of the initial intermediate representation, the child processes load the checkpoint data into respective memory spaces. The parent process produces incremental updates to the design checkpoint. The parent process signals availability of the incremental updates to the child processes, which apply the incremental updates to the checkpoint data in the respective memory spaces. The child processes process the circuit design in response to completion of producing incremental updates by the parent placer process.