Concurrent Code Processing with Selective SC-Atomic Conversion
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Solution Overview
Problem
In memory ordering hardware architectures, the inconsistency between actual code execution order and code writing order leads to potential risks such as crashes during execution, and existing solutions like inserting barrier instructions can cause additional processor operations or execution errors.
Innovation Solution
A code processing method that recognizes concurrency synchronization variables and converts their memory access code into SC-atomic memory access code, ensuring consistency between execution and writing orders, using techniques like pointer alias analysis to accurately identify and convert memory access code.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If barrier instructions are inserted into each loop to ensure sequential consistency, then code execution correctness is improved, but processor operation overhead increases and execution efficiency deteriorates
Solution Approach 1:
The patent applies local quality by differentiating between regular variables and concurrency synchronization variables. Only memory access operations on concurrency synchronization variables are converted to SC-atomic operations, while other memory operations remain unchanged. This selective approach ensures sequential consistency only where needed (for synchronization variables) rather than globally inserting barrier instructions everywhere, thus maintaining execution correctness for concurrent code while avoiding unnecessary processor overhead on non-critical paths.
Solution Approach 2:
The patent segments the code analysis process into distinct phases: concurrency synchronization variable recognition, memory access code identification, and selective conversion to SC-atomic operations. This segmentation allows the system to precisely target only the necessary portions of code that require sequential consistency, rather than applying barrier instructions uniformly across all loops and memory operations, thereby reducing overall execution overhead.
2Reliability
If static analysis is performed on abstract execution graphs to recognize loops, then sequential consistency is achieved, but loop recognition errors occur leading to incorrect fence insertion
Solution Approach 1:
Instead of starting with loop recognition and then determining which variables need synchronization, the patent inverts the approach by first identifying concurrency synchronization variables through their specific characteristics (annotated with volatile or atomic keywords, or identified as implicit synchronization variables in spin loops), and then selectively applying SC-atomic conversion only to memory access operations on these identified variables. This inversion eliminates the need for complex loop analysis while maintaining sequential consistency where actually needed.
Solution Approach 2:
The patent enables variables to self-identify as concurrency synchronization variables through specific annotations (volatile keyword, atomic keyword) or by their usage patterns (implicit synchronization variables in spin loops). This self-service mechanism allows the compiler to automatically recognize which variables require sequential consistency without requiring complex external analysis of loop structures and data dependencies, thereby improving both accuracy and automation.
3Reliability
If extra fence instructions are inserted due to incorrect loop recognition, then processor operations increase, but code execution errors are introduced
Solution Approach 1:
Concurrence synchronization variables self-identify through annotations (volatile, atomic keywords) or by their inherent usage patterns in spin loops. This self-service mechanism ensures that only variables that actually require synchronization are identified and processed, eliminating false positives that would lead to incorrect fence insertion and subsequent execution errors.
Solution Approach 2:
The patent extracts and isolates the identification of concurrency synchronization variables as a separate, focused task from the general loop analysis process. By extracting this specific identification logic (based on keywords and usage patterns) and applying SC-atomic conversion only to these extracted variables, the system avoids the harmful effect of inserting unnecessary or incorrect fence instructions that would arise from broader, less accurate loop-based analysis.
Data Source
AI summary
This application provides a code processing method and apparatus. The method includes: After obtaining first code corresponding to a source hardware architecture, a code processing apparatus performs concurrency synchronization variable recognition on the first code to obtain at least one concurrency synchronization variable; and then queries, from the first code, concurrency synchronization memory access code corresponding to each of the at least one concurrency synchronization variable, and may convert the concurrency synchronization memory access code corresponding to each of the at least one concurrency synchronization variable into corresponding SC-atomic memory access code. The SC-atomic memory access code corresponding to each of the at least one concurrency synchronization variable is used to generate target code applicable to a target hardware architecture.